參數(shù)資料
型號： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口)
中文描述： 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備）
文件頁數(shù)： 45/49頁
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PCI-SAR control and status registers
The PCI SAR has defined the following registers for status and control information.
OFFSET ADDRESS
(24 BIT HEX)
DESCRIPTION
WIDTH IN BITS
READ/WRITE
00E000
Software reset
32
Write only
00E004
SAR-status register
32
Read only
00E008
Interrupt-enable mask register
32
Read/write
00E010
Reserved
32
—
00E00C
SAR-configuration register
32
Read/write
00E014
BWG-table-size register
32
Read/write
00E018
Transmit/receive FIFO maximum-depth register
32
Read/write
00E01C
Reserved
32
—
00E020
Clear-transmit-freeze command
32
Write only
00E024
Clear-receive-freeze command
32
Write only
software-reset register (offset address 00E000h)
The PCI SAR reset operation is enabled when there is a hardware reset or when the host device writes into the
software-reset register. During a software-reset operation, the host reads initially the current status of the PCI
command/status register. The host writes to the PCI SAR software-reset register. Any value can be written into
the register by the host software. When the host writes into the software-reset register, the PCI SAR reset
operation is enabled. To reactivate the PCI SAR, the host has to write appropriate values in the PCI
command/status register.
PCI-SAR-status register (offset address 00E004h)
The PCI-SAR-status register is read only for the host. All the bits, except the transmit-freeze bit and the PCI-bus
error flags, are cleared when the register is read. The PCI SAR generates a PCI-bus interrupt to the host if one
of the bits in the register is set and if the condition represented by the bit is enabled by the interrupt-enable mask
register. The PCI-bus interrupt is an asynchronous signal that is held until the system clears the condition that
caused the interrupt. The bit format is shown in following table:
Reserved (bit 11)
Local-bus
Interrupt (bit 10)
Reserved (bit 9)
Reserved (bit 8)
Receive freeze (bit 7)
Transmit freeze (bit 6)
Transmit completion not
available (bit 5)
Receive completion not
available (bit 4)
Receive big-free buffer
not available (bit 3)
Receive small-free buffer
not available (bit 2)
Transmit completion
update (bit 1)
Receive completion
update (bit 0)
transmit completion update and receive completion update (bits 1–0)
The transmit or receive completion update bit is set when the hardware releases a transmit or receive descriptor,
respectively, to the completion ring. This is initiated when the OWN bits in the respective DMA blocks are cleared
by TNETA1561.
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