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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 11/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements (see Figure 4)
NO.
MIN
MAX
UNIT
1
tw(PCLKH)
Pulse duration, PCLK high
12
ns
2
tw(PCLKL)
Pulse duration, PCLK low
13
ns
3
tsu(PGNT)
Setup time, PGNT low before PCLK
↑
10
ns
4
tsu(PAD)
Setup time, PAD31–PAD0 valid before PCLK
↑
7
ns
5
tsu(PTRDY)
Setup time, PTRDY low before PCLK
↑
7
ns
6
tsu(PDEVSEL)
Setup time, PDEVSEL low before PCLK
↑
7
ns
7
th(PAD)
Hold time, PAD31 – PAD0 valid after PCLK
↑
2
ns
8
th(PTRDY)
Hold time, PTRDY low after PCLK
↑
2
ns
9
th(PDEVSEL)
Hold time, PDEVSEL low after PCLK
↑
2
ns
operating characteristics (see Figure 4)
NO.
MIN
MAX
UNIT
10
td(PFRAME)
Delay time, PCLK
↑
to PFRAME
↓
2
11
ns
11
td(PAD)
Delay time, PCLK
↑
to PAD31–PAD0 valid
2
11
ns
12
td(PCBE)
Delay time, PCLK
↑
to PCBE3–PCBE0 valid
2
11
ns
13
td(PIRDY)
Delay time, PCLK
↑
to PIRDY
↓
2
11
ns
14
td(PREQ)
Delay time, PCLK
↑
to PREQ
↓
2
12
ns
PCLK
(input)
PREQ
(output)
PGNT
(input)
PAD31–
PAD0
(I/O)
PFRAME
(output)
PCBE3–
PCBE0
(output)
PIRDY
(output)
PTRDY
(input)
PDEVSEL
(input)
4
Address
11
6
Bus Cmd
10
5
1
2
14
3
7
BE No. S-1
Data 1
Data 2
Data 3
BE No. S-2
Data 4
BE No. S-3
BE No. S-4
9
12
13
Data Phase
Address Phase
Turn-Around Cycle
8
Figure 4. TNETA1561 Read Operation (PCI SAR as Master)
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