參數(shù)資料
型號: TNETA1561
廠商: Texas Instruments, Inc.
英文描述: ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口)
中文描述: 自動柜員機分段和重組的PCI主機接口(自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備)
文件頁數(shù): 15/49頁
文件大?。?/td> 976K
代理商: TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics (see Figure 8)
NO.
MIN
TYP
30
MAX
UNIT
1
td(LBPHYCS)1
Delay time, LBRW
to LBPHYCS
ns
2
td(LBPHYCS)2
Delay time, LBADDR15–LBADDR0 valid to LBPHYCS
210
ns
3
td(LBPHYCS)3
Delay time, LBD7–LBD0 valid to LBPHYCS
30
ns
4
td(LBADDR)
Delay time, LBPHYCS
to LBADDR15–LBADDR0 invalid
150
ns
LBPHYCS is asserted low for eight PCI-clock cycles during a write operation to allow access to slow devices.
These values are given for operation with a 33-MHz PCI clock.
LBRW
(output)
LBRD
(output)
LBADDR15–
LBADDR0
(output)
LBD7–
LBD0
(output)
LBPHYCS
(output)
1
4
3
Figure 8. Local-Bus-Interface Write Operation (TNETA1561 as Slave)
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