參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 3/49頁(yè)
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
PCI-bus interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
PINTA
110
O
(open
drain)
PCI interrupt. PINTA is an interrupt request from PCI SAR.
PAD31–
PAD0
121–123,
125–129,
133–135,
138–141,
143,
156–159,
161–164,
167–170,
171,
173–175
I/O
(3 state)
PCI address bus and data bus. PAD31–PAD0 are multiplexed on the same PCI terminals.
During the first phase of a transaction (address phase), PAD31–PAD0 contains a 32-bit physical
address. This phase is the clock cycle when PFRAME is asserted.
During the data phase, PAD7–PAD0 contain the least significant byte and PAD31–PAD24
contain the most significant byte. Write data is stable when PIRDY is asserted. Read data is
stable when PTRDY is asserted. Data is transferred during those clock cycles when both PIRDY
and PTRDY are asserted.
PCBE3–
PCBE0
131, 144,
155, 165
I/O
(3 state)
PCI-bus command and byte enable. PCBE3–PCBE0 lines are multiplexed on the same PCI
terminals. During the address phase of a transaction, PCBE3–PCBE0 lines define the bus
command. During the data phase, PCBE3–PCBE0 lines define which bytes are valid.
PCLK
149
I
PCI clock. PCLK provides timing for all transactions on PCI.
PDEVSEL
151
I/O
(3 state)
PCI device select. PDEVSEL, when actively driven, indicates that the driving device has
decoded its address as the target of the current access. As an input, PDEVSEL indicates
whether any device on the bus is selected.
PFRAME
145
I/O
(3 state)
PCI frame. PFRAME is driven by the current master to indicate the beginning and duration of an
access. PFRAME is asserted at the beginning of the bus transaction and remains asserted
during data transfer. When PFRAME is deasserted, the transaction is in the final data phase.
PGNT
116
I
PCI bus grant. PGNT indicates to the agent that the arbiter has granted access to the bus. PGNT
is a point-to-point signal and every master has its own.
PCI initialization and device select. PIDSEL is used as a chip select during configuration read
and write transactions.
PCI initiator ready. PIRDY indicates the initiating agent’s (bus master) ability to complete the
current data phase of the transaction. During a write, PIRDY indicates valid data on
PAD31–PAD0. During a read, PIRDY indicates that the master is prepared to accept the data.
PIRDY is used with PTRDY when wait cycles are inserted until both PIRDY and PTRDY are
asserted.
PIDSEL
114
I
PIRDY
146
I/O
(3 state)
PPAR
154
I/O
PCI parity. PPAR is even across PAD31–PAD0 and PCBE3–PCBE0. For data phases, PPAR
is valid one clock after either PIRDY is asserted on a write or PTRDY is asserted on a read. Once
asserted PPARremainsvaliduntiloneclockafterthecompletionofthecurrentdataphase The
asserted, PPAR remains valid until one clock after the completion of the current data phase. The
master drives the PPAR for the address and write-data phases. The target drives PPAR for the
read-data phase.
(3 state)
PPERR
152
I/O
(3 state)
PCI parity error. PPERR reports a data-parity error on all commands except special cycle. An
agent cannot report a PPERR until it has claimed the access by PDEVSEL and completed a data
phase.
PREQ
111
O
PCI request. PREQ indicates to the arbiter that this agent desires use of the bus. Every master
has its own PREQ.
PRST
115
I
PCI reset. PRST forces the PCI sequence of each device to a known state.
PSERR
153
I/O
(open
drain)
PCI system error. PSERR reports address-parity errors and data-parity errors on special-cycle
commands.
PSTOP
177
I/O
(3 state)
PCI stop. PSTOP indicates the current target is requesting the master to stop the current
transaction.
PCI target ready. PTRDY indicates the target agent’s (selected device) ability to complete the
current data phase of the transaction. During a read, PTRDY indicates that valid data is present
on PAD31–PAD0. During a write, PTRDY indicates that the target is prepared to accept data.
PTRDY
147
I/O
(3 state)
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