- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385942 > TNETA1561 (Texas Instruments, Inc.) ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) PDF資料下載
參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 4/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
PCI SAR and local-bus interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
LBRESET
62
O
Local-bus reset. LBRESET is an active-high signal that is driven by the PCI SAR.
LBPHYCS
20
O
Local-bus PHY-layer chip select. LBPHYCS is used to interface with PHY-layer devices and is
driven by PCI SAR.
LBEPROMCS
19
O
Local-bus EPROM chip select. LBEPROMCS is an active-low signal that is driven by PCI SAR.
LBRW
63
O
Local-bus write. LBRW is an active-low write signal that indicates a write operation and is driven
by PCI SAR.
LBRD
61
O
Local-bus read. LBRD is an active-low read signal that indicates a read operation and is driven
by PCI SAR.
LBINTR
44
I
Local-bus interrupt. LBINTR is an interrupt that is generated and driven by a local-bus device.
LBREADY
45
I
Local-bus ready. LBREADY is driven by local-slave devices. The bus transaction is completed
after eight PCI bus cycles regardless of LBREADY. LBREADY is accepted by the SAR as a
handshake from the devices on the bus.
LBD7–
LBD0
59,
55–53,
51–48
I/O
Local-bus data. LBD7–LBD0 are used to transfer data to and from local-slave devices and are
driven by PCI SAR or local-slave devices.
LBADDR15–
LBADDR0
43–42,
39–35,
33–29,
27–24
O
Local-bus address. LBADDR15–LBADDR0 are driven by the PCI SAR and are used to address
the PHY-layer registers and the EPROM. LBADDR15–LBADDR2 are received from the PCI bus
and LBADDR1–LBADDR0 are generated by the PCI SAR.
PHY-layer receive interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
RCLK
84
O
Receive clock. RCLK is equivalent to the internal clock at 19.44 MHz. RCLK is sent to the PHY
layer.
RDATA7–
RDATA0
78,
75–72,
69–67
I
Receive data. RDATA7–RDATA0 are connected to the PHY-layer receive interface and are
driven by the PHY-layer device.
RSOC
81
I
Receive start of cell. RSOC is a signal from the PHY layer indicating that the first byte of an ATM
cell was sent to the TNETA1561.
RXEMPTY
80
I
Receive buffer empty in the PHY layer. RXEMPTY is a signal that acts as an inverted enable
signal on this interface and is driven by the PHY layer.
RXENABLE
85
O
Receive enable. RXENABLE is active low and is driven by the TNETA1561.
相關PDF資料 |
PDF描述 |
|---|---|
| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
發(fā)布緊急采購，3分鐘左右您將得到回復。