- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385942 > TNETA1561 (Texas Instruments, Inc.) ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) PDF資料下載
參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 31/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
packet length (bits 26 – 16)
The packet-length field is expressed in units of cells in the packet. The host computes the correct number of
cells in the packet including additional cells that are sometimes needed for AAL5 to accommodate the 8-byte
tail. This field represents the value used by the PCI SAR in silicon to determine the number of cells in a packet
and enable EOP processing. The field is programmed in two’s complement. Incrementing the value by one each
time a cell is sent results in zero when the entire packet is transmitted. The maximum size of a packet is
64K bytes; therefore,11 bits are adequate to describe the largest packet.
Since this is a packet-level field as opposed to one that applies to individual buffers, it is placed only in the first
buffer descriptor of a packet in the transmit data-descriptor rings. The DMA channel only updates the
packet-length field on a per-packet basis. The packet-length field is used for all three AAL modes that are
supported. In each case, the PCI SAR enables EOP processing to notify the host when the EOP is detected
on transmit via the packet-length field.
buffer length (bits 15 – 0)
The buffer-length field specifies the number of bytes in the buffer represented by this descriptor-ring entry. The
maximum buffer size is 64K bytes, which is the largest packet size and allows an entire packet in one buffer.
This field is programmed in two’s complement and is equal to zero when all the bytes in a buffer are retrieved
by the PCI SAR.
TX descriptor-ring word 1 – start-of-buffer pointer
Byte-aligned start-of-buffer pointer (bits 31 – 0)
The start-of-buffer pointer is 32 bits. Each buffer is aligned on byte boundaries.
TX descriptor-ring word 2 – ATM header
PTI (bits 31 – 29)
CLP (bit 28)
VPI (bits 27 – 20)
VCI (bits 19 – 4)
PTI (bits 3 – 1)
CLP (bit 0)
Word 2 contains the 4-byte header for every cell of the packet. The upper-order four bits of the ATM header,
representing the GFC at the user-to-network interface (UNI), are set to zero in every outgoing cell. Bits (3 – 0)
in word 2 represent the payload-type indicator (PTI) and cell-loss priority (CLP) fields used in every cell of the
packet except the last one (the cell that contains the EOP indication). Bits (31 – 28) in word 2 represent the PTI
and CLP fields used in the last cell of the packet.
The PTI field in the last cell of the AAL5 packet is set either to 001 or 011. The CLP is programmable and the
cell containing the EOP indication can have a different priority level from the other cells. This field is required
only in the first descriptor for the packet. In AAL3/4 or null-AAL packets, the PTI and CLP fields are the same
in both the upper- and lower-order bits of word 2.
BITS
PLACE IN ATM HEADER
3–0
Least-significant four bits of byte 4 of 5-byte ATM header
7–4
Most-significant four bits of byte 4 of 5-byte ATM header
15–8
Byte 3 of 5-byte ATM header
19–16
Least-significant four bits of byte 2 of 5-byte ATM header
23–20
Most-significant four bits of byte 2 of 5-byte ATM header
27–24
Least-significant four bits of byte 1 of 5-byte ATM header
相關PDF資料 |
PDF描述 |
|---|---|
| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
發(fā)布緊急采購，3分鐘左右您將得到回復。