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| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 37/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
packet length (bits 10–0)
The packet-length field in word 0 is set up with the two’s-complement value for the buffer size in cells used by
this BWG at the start of each new packet. The counter is incremented with each new cell until the EOP signal
or the value is zero. Null-AAL packets are terminated when the value of this counter reaches zero. If either the
AAL5 or AAL3/4 packet fills the buffer to capacity, the counter reaches zero and the packet is terminated with
the buffer-overflow indicator set in the receive-completion-ring entry.
RX DMA word 1 – current-buffer pointer
Unused (bits 31–28)
Current-buffer pointer – 16 byte aligned (bits 27–0)
The current-buffer pointer is 28 bits, which implies that the buffer is aligned to 16-byte boundaries. This is a
dynamic field that is updated with every RCB-to-PCI-bus transaction.
RX DMA word 2 – start-of-buffer pointer
Unused (bits 31–28)
Start-of-buffer pointer – 16 byte aligned (bits 27–0)
The start-of-buffer pointer is 28 bits because the buffer is aligned to 16-byte boundaries. This field is copied from
the corresponding 28-bit field in word 0 of a free-buffer-ring entry.
RX DMA word 3 – configuration
Configuration (bits 31–23)
Unused (bits 22–11)
Null-AAL packet length (bits 10–0)
OWN bit position (bit 31)
The OWN bit is set high for each valid receive channel. It is copied into the corresponding OWN bit location in
word 0 at the start of each new packet to indicate that the DMA channel is active. This OWN bit is automatically
reset to a 0 after the end-of-packet indicator is received.
VC_ON (bit 30)
The VC_ON bit enables packet-reassembly processing. The bit is set in the default mode to indicate that the
VC is enabled. The PCI SAR discards cells received on the corresponding VC when the VC_ON bit is
deasserted on a per-cell basis.
buffer type – small or big (bit 29)
The PCI SAR supports only two buffer sizes on receive: small and big. The host determines the sizes of the small
and big buffers. The buffer-type bit is used to select between a buffer pointer from the small free-buffer ring or the
big free-buffer ring for each new packet, which allows the host to target small or big buffers for all packets on a
given VC. The small free-buffer ring is used when the bit is set and the big free-buffer ring is used in the default
(zero) state.
null-AAL indication (bit 28)
This field is set to indicate that null-AAL packets are received on this BWG (VC). The null-AAL packet-length
field in bits (10–0) is used to determine the end of a packet. CRC errors are ignored for null-AAL packets. The
CRC-error indicator in the receive completion ring is not used.
AAL3/4 indication (bit 25)
This field is set to indicate that AAL3/4 packets are received on this BWG (VC). This indicates the EOM field
in byte 6 (bit 6 of an ATM cell is used as the EOP indicator). CRC errors are ignored for AAL3/4 packets. The
CRC-error indicator in the receive completion ring is not used.
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