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| 型號(hào)： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 46/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive big free-buffer not available and receive small free-buffer not available (bits 3–2)
The appropriate receive free-buffer not-available bit is set when the first entry in the corresponding receive
free-buffer ring is not available. This is indicated when the OWN bit in the first entry of the free ring is zero. The
incoming cell is deleted because there is no buffer available to hold it. This eventually causes the loss of the
entire packet due to the resultant CRC error. The buffer allocation-error bit in the DMA block is set. This is
indicated by a zero in the first free-buffer ring entry.
receive completion-ring not available (bit 4)
The receive completion-ring not-available bit is set when the next descriptor in the receive completion ring is
not released by the host. This is indicated when the OWN bit in the entry is zero (host owns it). This packet and
buffer are both lost to host memory.
transmit completion-ring not available (bit 5)
The transmit completion-ring not-available bit is set when the next descriptor in the transmit completion ring is
not released by the host. This is indicated when the OWN bit in the entry is zero. The transmit-freeze bit is set
when this bit is set, disabling all transmit operation until the transmit-freeze bit is cleared via an active command
from the host.
transmit freeze (bit 6)
The transmit-freeze bit is set when the transmit completion-ring not-available bit is set, disabling all transmit
operation until the transmit-freeze bit is cleared via an active command from the host. This has the same effect
on the transmit circuitry as disabling the enable-transmit bit.
receive freeze (bit 7)
The receive-freeze bit is set when the receive completion-ring not-available bit is set, disabling all receive
operation until the receive-freeze bit is cleared via an active command by the host. The buffer that could not
be posted is effectively lost, and the host must find some way to recover it while the freeze is in operation. The
receive-freeze indicator has the same effect on the receive path as disabling the enable-receive bit.
reserved (bit 8)
reserved (bit 9)
local-bus interrupt (bit 10)
The local-bus interrupt bit is set if an interrupt is generated on the local bus.
reserved (bit 11)
interrupt-enable mask register (offset address 00E008h)
Unused (bits 31–12)
Mask bits (bits 11–0)
An interrupt-enable mask-register bit has a bit that corresponds to every entry in the PCI-SAR status register.
When a bit is set in the status register, an interrupt is generated if a corresponding bit in the interrupt-enable
mask register is also set.
SAR-configuration register (offset address 00E00Ch)
The SAR-configuration register holds various values pertaining to the overall PCI-SAR configuration. The host
can read the register and is allowed to program the EN receive and the EN transmit bits. In addition, two more
bits are defined for posted write-buffer enable (PWBE) and software reset (SR).
Unused (bits 31–5)
SDH (bit 5)
Unused (bits 4–3)
EN receive (bit 2)
EN transmit (bit 1)
0 (bit 0)
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