參數(shù)資料
型號: TNETA1561
廠商: Texas Instruments, Inc.
英文描述: ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口)
中文描述: 自動柜員機分段和重組的PCI主機接口(自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備)
文件頁數(shù): 17/49頁
文件大?。?/td> 976K
代理商: TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Operation
Data Structure
Registers
23
28
39
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Table of Contents
Functional Overview
Functional Description
Interfaces
17
18
21
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functional overview (see Figure 11)
The TNETA1561 (PCI SAR) implements the PCI-bus protocols for connecting a peripheral device to a PCI-bus
host system (mapped in memory space) and is designed for the PCI plug-in card concept. The central-resource
functions, such as PCI-bus arbitration, are implemented by the host processor using the PCI SAR adapter.
The PCI SAR provides the PCI-configuration space to support its configuration and initialization. This
configuration space specifies data for initialization software and error-handling software. The PCI SAR supports
the mechanism to implement an external-EPROM interface for device-specific initialization and other booting
mechanisms.
The PCI bus uses bursts as the basic mechanism to transfer data. The TNETA1561 supports data-burst sizes
up to 52 bytes for a PCI-bus access requiring a total of 13 data-phase transfers. A 13-word data transfer occurs
when the payload data is not 32 bit aligned. The typical latency for PCI-bus access is 2
μ
s, but this PCI SAR
provides adequate data buffering for a worst-case latency of up to 30
μ
s.
Host
CPU
Memory
Master
Arbiter
Bus
Bridge
PCI
Bus
32
TNETA1561
(PCI SAR)
EPROM
Physical
Layer
Media
8
Local Bus
Control
Memory
32
Control-Bus
Memory
TX UTOPIA
RX UTOPIA
Figure 11. TNETA1561 Architecture
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