參數(shù)資料
型號： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口)
中文描述： 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備）
文件頁數(shù)： 25/49頁
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PCI-bus physical addresses for PCI SAR peripheral devices
The data below specifies the PCI SAR slave-mode PCI-bus physical-address ranges for peripheral devices.
DESCRIPTION
ADDRESS BITS
14
14
14
READ/WRITE REGISTER
R
R/W
R/W
EPROM addresses
PHY-layer register addresses
Control-memory addresses
packet-interface information
Packet interface, BWG-table mechanism, AAL5 processing, AAL3/4 processing, null-AAL processing,
VPI/VCI/GFC processing, OAM processing, and details on the transmit-descriptor rings/DMA, receive
free-buffer rings/DMA, and completion rings is described in this section.
The PCI SAR uses host memory to store a packet (48-byte cells) in both transmit and receive directions. The
PCI SAR initiates the data transfer for the PCI bus for both transmit and receive operations. The packet does
not include AAL5 encapsulation while in host memory. The PCI SAR provides this header data. The buffering
of data within the PCI SAR is limited to an 8-cell FIFO for transmit and a 32-cell FIFO for receive.
Each packet queued for transmission can be distributed across multiple buffers in host memory with each
starting on a one-byte boundary. Packets that are received over ATM are placed in a single buffer in host
memory (either big or small) aligned to a 16-byte boundary.
bandwidth group (BWG) table mechanism
The PCI SAR generates data via a special bit-rate control table known as the BWG table (see Figure 14). The
BWG table consists of up to 4800 entries and each entry consists of an 8-bit BWG index. The table is organized
with 1200 words in control memory. The size is programmable via the BWG-size register. Each BWG index
corresponds to a transmit DMA channel, and the TNETA1561 can support 255 (8-bit index) transmit DMA
channels simultaneously. The PCI SAR cycles through the table and sends an ATM cell for the transmit DMA
channel for each entry in the table. If a zero value is entered for a BWG index, an idle cell is transmited. The
BWG table assigns the transmit-side bandwidth. The total available bandwidth for an OC-3c SONET link is
135.63 Mbit/s (155.52 Mbit/s less SONET and ATM overhead). The granularity is obtained by dividing the
SONET-link bit rate (135.63 Mbit/s) by the entries in the BWG table (4800).
135.63 Mbit/s
÷
4800 = 28,250 bit/s per entry
An application requiring 500 kbit/s requires 19 entries in the table.
500 kbit/s
÷
28,250 bit/s per entry = 19 required entries in the table
相關(guān)PDF資料
PDF描述
TNETA1600 SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TNETA1561PGC 制造商:Rochester Electronics LLC 功能描述:- Bulk
TNETA1570 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
TNETA1570MFP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit
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TNETA1575 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES
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