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| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 28/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit descriptor rings and DMA (continued)
Each descriptor-ring entry contains a control bit that indicates whether a buffer is queued up for transmission.
The DMA entry for each BWG contains a pointer to the first item in the queue in the corresponding descriptor
ring. An idle cell is transmitted if the control bit in the descriptor entry indicates an inactive entry. The DMA entry
has a bit that allows the host to disable any BWG.
receive free-buffer rings and DMA
The PCI SAR uses buffer pointers from two free-buffer rings to place the incoming packet data in the host
memory. These are called small free-buffer ring and big free-buffer ring. Each receive BWG has a control bit
indicating the type of buffer it uses: small or big. These buffers are preallocated by the host application for the
next packet and not by the BWG.
The PCI SAR supports 1023 receive DMA channels and 1023 VCIs. The incoming VCI indexes the receive DMA
channels. BWG 0 is reserved to process information for OAM cells.
completion rings
The PCI SAR indicates completion of packet processing in either direction to the host via an interrupt and by
posting entries to receive and transmit completion rings. Each completion ring accepts up to 256 entries. A
control bit in each entry of the completion ring prevents the PCI SAR from overwriting an entry that has not been
processed by the host.
data structure
The PCI SAR data structure and contents of various physical locations are summarized below:
CONTROL MEMORY
HOST MEMORY
INTERNAL REGISTERS
BWG table
TX descriptor rings (255)
PCI SAR operational registers
TX DMA states
TX completion ring
PCI SAR configuration registers
RX DMA states
Small free-buffer ring
PCI configuration space
Initialization block
Big free-buffer ring
RX completion ring
Data buffers
The parameters necessary for booting the device are stored in the PCI configuration space. Some systems may
use an external EPROM that contains the booting sequence.
The system has a bus width of four bytes and all transactions are conducted on 4-byte boundaries. The PCI
SAR uses little-endian addressing as a PCI-bus device. Each descriptor ring has 256 entries and each
descriptor-ring entry consists of four words. Each descriptor ring is aligned to a 4K-byte boundary in host
memory with each entry aligned to a 16-byte boundary.
The PCI SAR has two receive free-buffer rings, one transmit completion ring, and one receive completion ring.
The current pointer to each of these rings is stored in the initialization block in the control memory. An entry in
each transmit DMA channel points to one of the 255 transmit descriptor rings in host memory.
Each DMA-channel entry consists of eight words and is located in control memory. The DMA entries on both
transmit and receive have an OWN bit that is set when the DMA channel is active. The descriptor-ring entries,
the completion-ring entries, and the free-buffer ring entries have an OWN bit that is set when the entry belongs
to the PCI SAR.
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