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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組的PCI主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 34/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TX DMA word 3 – configuration
BWG_ON (bit 31)
Unused (bits 30–0)
This bit allows the host to enable data transmission on a per-BWG basis. The BWG_ON bit from the current
BWG index is examined by the PCI SAR on each cell opportunity. BWG_ON (31) is directly set by the host to
indicate that the BWG is enabled and that normal data processing is followed. If the bit is zero, no processing
of transmit data on the BWG is performed and an idle cell is transmitted on the link. This idle cell is used by the
host to respond to congestion indicators.
TX DMA word 4 – descriptor-ring address
TX-data descriptor-ring pointer (bits 31–12)
TX descriptor-ring entry (bits 11–4)
0000 (bits 3–0)
This pointer is a DMA address to the location of the current entry (there are 256 entries in each ring) in the
corresponding transmit data-descriptor ring (one of 255 rings) for this BWG. Each descriptor ring is aligned to
a 4K-byte boundary in host memory with each entry aligned to a 16-byte boundary.
The address of the 4K-byte boundary in host memory is provided by bits (31–12). The entry number between
0 and 255 is provided by bits (11–4). The low-order four bits are set to zero and each entry is 16 byte aligned.
Bits (11–0) are initialized by the host to zero to correspond with the first entry used by the host in the transmit
data-descriptor ring.
TX DMA word 5 – reserved
Reserved
TX DMA word 6 – transmit CRC
Partial AAL5 transmit CRC (bits 31–0)
This field stores the 32-bit CRC calculated over the entire payload of each AAL5 packet. The CRC is placed
in the last four bytes of the last cell of the corresponding packet.
TX DMA word 7 – AAL5 tail
AAL5 control field (bits 31 – 16)
AAL5 length field (bits 15 – 0)
The AAL5 control and length fields are copied directly from the corresponding transmit data-descriptor entry
at the start of each new packet. The length field is not used for any control functions within the PCI SAR. Both
fields are used exclusively for placement in the tail of an AAL5-protocol data unit (PDU).
transmit completion ring
This entry contains only one word. The transmit completion ring is a descriptor ring with 256 entries. The PCI
SAR posts an item to the next entry in the completion ring when it completes the transmission of each packet.
The transmit-completion-ring pointer maintains the value of the current entry within the PCI SAR. The host can
recalibrate to this by reading the value from the initialization block in control memory.
transmit-completion-ring summary
ENTRY
DESCRIPTION
Word 0
OWN (bit 31)
Unused (bits 30–8)
BWG index (bits 7–0)
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