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| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組的PCI主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 33/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
start of chain (SOC) (bit 30)
The SOC bit indicates that this is the first buffer of a packet which consists of one or more buffers. The SOC
bit is also set in packets with single buffers. The SOC bit is cleared by the PCI SAR after all processing for the
first buffer is complete.
end of chain (EOC) (bit 29)
The EOC bit indicates that this is the last buffer of a packet. Every packet has at least one buffer with the EOC
bit set.
AAL-type – AAL5 indicator (bit 27)
The AAL-type bit is set to zero to indicate that the packet described in this descriptor-ring entry is an AAL5
packet. This bit is a configuration item rather than a bit carrying state information. This bit is set in every buffer
of a packet and the software driver must ensure that all the buffers in a packet use the same AAL type.
current-packet length (bits 26–16)
The PCI SAR increments this two’s-complement value with every cell transmitted until the counter is equal to
zero, which indicates to the PCI SAR that the entire packet has been transmitted.
current-buffer length (bits 15–0)
The buffer-length field specifies the number of remaining bytes in the buffer currently being processed in this
BWG. The PCI SAR adds to the value of this two’s-complement field with every transfer of payload data to the
XMB until it is equal to zero, which indicates to the PCI SAR that all the bytes in this buffer are processed and
queued for transmission.
TX DMA word 1 – current-buffer pointer
Byte-aligned current-buffer pointer (bits 31–0)
The current-buffer pointer is copied directly from the start-of-buffer pointer in the corresponding transmit
data-descriptor-ring entry at the start of each new buffer. The field is 32 bits, which implies that the buffer is
aligned to a byte boundary. The pointer is adjusted to point to the current location after each transfer of payload
data from the host to the XMB.
TX DMA word 2 – ATM header
PTI (bits 31 – 29)
CLP (bit 28)
VPI (bits 27 – 20)
VCI (bits 19 – 4)
PTI (bits 3–1)
CLP (bit 0)
The 4-byte ATM header field is copied directly from the corresponding transmit data-descriptor entry at the start
of each new packet. Bits (28–0) are concatenated to the 4-bit GFC field that is set to zero for every cell in the
packet except the last one. Bits (31–28) provide the PTI and CLP fields in the last cell of each packet.
BITS
PLACE IN ATM HEADER
3–0
Least-significant four bits of byte 4 of 5-byte ATM header
7–4
Most-significant four bits of byte 4 of 5-byte ATM header
15–8
Byte 3 of 5-byte ATM header
19–16
Least-significant four bits of byte 2 of 5-byte ATM header
23–20
Most-significant four bits of byte 2 of 5-byte ATM header
27–24
Least-significant four bits of byte 1 of 5-byte ATM header
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