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參數資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數： | 2/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PGC PACKAGE
(TOP VIEW)
LBRD
LBRESET
LBRW
GND
V
CC
NC
RDATA0
RDATA1
RDATA2
V
CC
GND
RDATA3
RDATA4
RDATA5
RDATA6
GND
V
CC
RDATA7
TXFULL
RXEMPTY
RSOC
V
CC
GND
RCLK
RXENABLE
TDATA0
TDATA1
GND
V
CC
TDATA2
TDATA3
TDATA4
TDATA5
V
CC
GND
TDATA6
TDATA7
TSOC
TCLK
GND
V
CC
TXENABLE
NC
NC
NC
V
CC
GND
NC
NC
PINTA
PREQ
GND
V
CC
PIDSEL
PRST
PGNT
GND
V
CC
NC
NC
CMD31
CMD30
V
GND
CMD29
CMD28
CMD27
CMD26
GND
CMD25
CMD24
CMD23
CMD22
CMD21
V
CMD20
CMD19
CMD18
CMD17
CMD16
GND
CMD15
CMD14
CMD13
CMD12
CMD11
V
CMD10
CMD9
CMD8
CMD7
CMD6
GND
CMD5
CMD4
CMD3
CMD2
CMD1
V
CMD0
NC
NC
NC
NC
GND
CMOE
CMR/W
NC
NC
GND
V
CC
NC
NC
NC
NC
SCANEN
GND
NC
NC
TESTMODE
N
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
239
237
235
233
231
229
227
225
223
221
219
217
215
213
211
209
207
205
203
201
199
197
195
193
191
189
187
185
183
181
L
V
P
G
L
L
L
G
L
L
L
L
G
L
L
L
L
G
L
L
L
L
L
L
L
L
L
L
G
L
L
L
L
G
N
L
L
C
C
G
C
C
C
C
C
C
C
G
C
C
C
N
P
G
P
P
P
P
P
C
P
N
P
P
P
G
P
P
P
P
P
P
P
P
P
G
P
P
P
P
P
P
P
P
P
P
G
P
P
P
P
P
P
P
P
P
P
G
P
P
P
G
P
N
N
P
P
C
V
C
V
C
V
C
V
C
V
C
C
V
C
V
C
V
C
V
C
V
5
5
5
5
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
9
7
5
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
V
C
NC – No internal connection
description (continued)
The native clock for the TNETA1561 is the PCI clock, which operates up to 33 MHz. The native-word size for
the device is 32 bits, corresponding to the data width for the PCI bus. The TNETA1561 host interface implements
the bus protocol defined in the PCI-local-bus specification (revision 2.0). The control-memory interface is 32
bits wide. This interface allows the device to access the local memory to obtain the control information on the
packets being segmented and reassembled and to obtain their locations in host memory. Each packet queued
for transmission can be distributed across multiple buffers in host memory with each starting at any byte
boundary. This is supported in hardware by the device. Every received package is placed in a single buffer in
the host memory and is aligned to a 16-byte boundary. The TNETA1561 operation is explained in detail in the
Principles of Operation section.
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PDF描述 |
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| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
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