參數(shù)資料
型號： TSPC603R
英文描述： TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述： TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫
文件頁數(shù)： 14/44頁
文件大小： 636K
代理商： TSPC603R
14
TSPC603R
2125A
–
HIREL
–
04/02
Bus snooping and time base/decrementer still enabled.
Dose mode sequence:
- Set doze bit (HID0[8) = 1).
- 603r enters doze mode after several processor clocks.
Several methods of returning to full-power mode:
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
Transition to full-power state takes no more than a few processor cycles.
PLL running and locked to SYSCLK.
Nap Mode:
The nap mode disables the 603r but still maintains the phase locked loop
(PLL) and the time base/decrementer. The time base can be used to restore the 603r to
full-on state after a programmed amount of time. Because bus snooping is disabled for
nap and sleep mode, a hardware handshake using the quiesce request (QREQ) and
quiesce acknowledge (QACK) signals are requires to maintain data coherency. The
603r will assert the QREQ signal to indicate that it is ready to disable bus snooping.
When the system has ensured that snooping is no longer necessary, it will assert QACK
and the 603r will enter the sleep or nap mode.
Time base/decrementer still enabled.
Most functional units disabled (including bus snooping).
All nonessential input receivers disables.
Nap mode sequence:
- Set nap bit (HID0[9] = 1)
- 603r asserts quiesce request (QREQ) signal
- System asserts quiesce acknowledge (QACK) signal
- 603r enters sleep mode after several processor clocks
Several methods of returning to full-power mode:
- Assert INT, SPI, MCP or decrementer interrupts
- Assert hard reset or soft reset
Transition to full-power takes no more than a few processor cycles.
PLL running and locked to SYSCLK.
Sleep Mode:
Sleep mode consumes the least amount of power of the four modes since
all functional units are disabled. To conserve the maximum amount of power, the PLL
may be disabled and the SYSCLK may be removed. Due to the fully static design of the
603r, internal processor state is preserved when no internal clock is present. Because
the time base and decrementer are disabled while the 603r is in sleep mode, the 603r
’
s
time base contents will have to be updated from an external time base following sleep
mode if accurate time-of-day maintenance is required. Before the 603r enters the sleep
mode, the 603r will assert the QREQ signal to indicate that it is ready to disable bus
snooping. When the system has ensured that snooping is no longer necessary, it will
assert QACK and the 603r will enter the sleep mode.
All functional units disabled (including bus snooping and time base).
All nonessential input receivers disabled:
- Internal clock regenerators disabled
- PLL still running (see below)
Sleep mode sequence:
- Set sleep bit (HID0[10] = 1)
- 603r asserts quiesce request (QREQ)
- System asserts quiesce acknowledge (QACK)
- 603r enters sleep mode after several processor clocks
相關(guān)PDF資料
PDF描述
TSPC750AMGS10LH Microprocessor
TSPC750AMGS12LE Microprocessor
TSPC750AMGSU10LE Microprocessor
TSPC750AMGSU10LH Microprocessor
TSPC750AMGSU12LE Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSPC603RCAB/Q8L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RCAB/Q8LC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8LC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMG10LC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*