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| 型號(hào)： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 24/44頁 |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
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24
TSPC603R
2125A
–
HIREL
–
04/02
Special-Purpose Registers
(SPRs)
The PowerPC operating environment architecture defines numerous special-purpose
registers that serve a variety of functions, such as providing controls, indicating status,
configuring the processor, and performing special operations. During normal execution,
a program can access the registers, shown in Figure 13, depending on the program
’
s
access privilege (supervisor or user, determined by the privilege-level (PR) bit in the
MSR). Note that register such as the GPRs and FPRs are accessed through operands
that are part of the instructions. Access to registers can be explicit (that is, through the
use of specific instructions for that purpose such as Move to Special-Purpose Register
(MTSPR) and Move from Special-Purpose Register (MTSPR) instructions) or implicit, as
the part of the execution of an instruction. Some registers are accessed both explicitly
and implicitly.
Il the 603r, all SPRs are 32 bits wide.
USER-LEVEL SPRs:
The following 603r SPRs are accessible by user-level software:
Link Register (LR) - The link register can be used to provide the branch target
address and to hold the return address after branch and link instructions. The LR is
32 bits wide in 32-bit implementations.
Count Register (CTR) - The CRT is decremented and tested automatically as a
result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit
implementations.
Integer Exception Register (XER) - The 32-bit XER contains the summary overflow
bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be
transferred by a Load String Word Indexed (LSWX) or Store String Word Indexed
(STSWX) instruction.
SUPERVISOR-LEVEL SPRs:
The 603r also contains SPRs that can be accessed only
by supervisor-level software. These registers consist of the following:
The 32-bit DSISR defines the cause of data access and alignment exceptions.
The data address register (DAR) is a 32-bit register that holds the address of an
access after an alignment or DSI exception.
Decrementer register (DEC) is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay.
The 32-bit SDR1 specifies the page table format used in virtual-to-physical address
translation for pages. (Note that physical address is referred to as real address in
the architecture specification).
The machine status Save/Restore Register 0 (SRR0) is a 32-bit register that is used
by the 603r for saving the address of the instruction that caused the exception, and
the address to return to when a Return from Interrupt (
RFI
) instruction is executed.
The machine status save/restore register 1 (SRR1) is a 32-bit register used to save
machine status on exceptions and to restore machine status when an
RFI
instruction is executed.
The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
The external access register (EAR) is a 32-bit register that controls access to the
external control facility through the External Control In Word Indexed (
ECIWX
) and
External Control Out Word Indexed (
ECOWX
) instructions.
The time base register (TB) is a 64-bit register that maintains the time of day and
operates interval timers. The TB consists of two 32-bit fields - time base upper
(TBU) and time base lower (TBL).
The processor version register (PVR) is a 32-bit, read-only register that identifies
the version (model) and revision level of the PowerPC processor.
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| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
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