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參數(shù)資料
| 型號(hào)： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
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33
TSPC603R
2125A
–
HIREL
–
04/02
Program
00700
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
Floating-point enabled exception
—
A floating-point enabled exception condition is
generated when the following condition is met: (MSR[FE0] | MSR[FE1]) & FPSCR[FEX]
FPSCR[FEX] is set by the execution of a floating-point instruction that causes an enabled
exception or by the execution of one of the
“
move to FPSCR
”
instructions that results in
both an exception condition bit and its corresponding enable bit being set in the FPSCR.
Illegal instruction
—
An illegal instruction program exception is generated when execution
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the 603e), or
when execution of an optional instruction not provided in the 603e is attempted (these do
not include those optional instructions that are treated as no-ops).
Privileged instruction
—
A privileged instruction type program exception is generated
when the execution of a privileged instruction is attempted and the MSR register user
privilege bit, MSR[PR], is set. In the 603e, this exception is generated for mtspr or mfspr
with an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all
PowerPC processors.
Trap
—
A trap type program exception is generated when any of the conditions specified
in a trap instruction is met.
Floating-point
unavailable
00800
A floating-point unavailable exception is caused by an attempt to execute a floating-point
instruction (including floating-point load, store, and more instructions) when the floating-
point available bit is disabled, (MSR[FP] = 0).
Decrementer
00900
The decrementer exception occurs when the most significant bit of the decrementer (DEC)
register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
Reserved
00A00
–
00BFF
—
System call
00C00
A system call exception occurs when a System Call (sc) instruction is executed.
Trace
00D00
A trace execution is taken when MSR[SE] = 1 or when the currently completing instruction
is a branch and MSR[BE] = 1.
Reserved
00E00
The 603e does not generate an exception to this vector. Other PowerPC processors may
use this vector for floating-point assist exceptions.
Reserved
00E10
–
00FFF
—
Instruction
translation miss
01000
An instruction translation miss exception is caused when an effective address for an
instruction fetch cannot be translated by the ITLB.
Data load
translation miss
01100
A data load translation miss exception is caused when an effective address for a data load
operation cannot be translated by the DTLB.
Data store
translation miss
01200
A data store translation miss exception is caused when an effective address for a data
store operation cannot be translated by the DTLB; or where a DTLB hit occurs, and the
change
Instruction address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0-29) in the
IABR matches the next instruction to complete in the completion unit, and the IABR enable
bit (bit 30) is set to 1.
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI input signal is
asserted.
Reserved
01500
–
02FFF
—
Table 16.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
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| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
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