參數(shù)資料
型號: TSPC603R
英文描述: TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述: TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫
文件頁數(shù): 31/44頁
文件大小: 636K
代理商: TSPC603R
31
TSPC603R
2125A
HIREL
04/02
After the exception handler handles an exception, the instruction execution continues
until the next exception condition is encountered. However, in many cases there is no
attempt to re-execute the instruction. This method of recognizing and handling excep-
tion conditions sequentially guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to pre-
vent the program state from being lost due to a system reset and machine check
exception or to an instruction-caused exception in the exception handler, and before
enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
Synchronous, precise
- These are causes by instructions. All instruction-caused
exceptions are handled precisely; that is, the machine state at the time the
exception occurs is known and can be completely restored. This means that
(excluding the trap and system call exceptions) the address of the faulting
instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution
before the exception is taken. Once the exception is processed, execution resumes
at the address of the faulting instruction (or at an alternate address provided by the
exception handler). When an exception is taken due to an trap or system call
instruction, execution resumes at an address provided by the handler.
Synchronous, imprecise
- The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. Even though the
603r provides a means to enable he imprecise modes, it implements these modes
identically to the precise mode (-hat is, all enabled floating-point enabled exceptions
are always precise on the 603r).
Asynchronous, maskable
- The external, SMI, and decrementer interrupts are
maskable asynchronous exceptions. When these exceptions occur, their handling is
postponed until the next instruction, and any exceptions associated with that
instruction, completes execution. If there are no instructions in the execution units,
the exception is taken immediately upon determination of the correct restart address
(for loading SRR0).
Asynchronous, nonmaskable
- There are two non maskable asynchronous
exceptions: system reset and the machine check exception. These exceptions may
not be recoverable, or may provide a limited degree of recoverability. All exceptions
report recoverability through the SMR[RI] bit.
PowerPC 603rMicroprocessor
Exception Model
A specified by the PowerPC architecture, all 603r exceptions can be described as either
precise or imprecise and either synchronous or asynchronous. Asynchronous excep-
tions (some or which are maskable) are caused by events external to the processor
s
execution; synchronous exceptions, which are all handled precisely by the 603r, are
caused by instructions. The 603r exception classes are shown in Table 15.
Table 15.
PowerPC 603r Microprocessor Exception Classifications
Synchronous/Asynchronous
Precise/Imprecise
Exception Type
Asynchronous, Non Maskable
Imprecise
Machine check
System reset
Asynchronous, Maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
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