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| 型號： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 636K |
| 代理商： | TSPC603R |
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TSPC603R
2125A
–
HIREL
–
04/02
Integer instructions operate on byte, half-word, and word operands. Floating-point
instructions operate on single-precision (one word) and double-precision (one double
word) floating-point operands. The PowerPC architecture uses instructions that are four
bytes long and word-aligned. It provides for byte, half-word, and word operand loads
and stores between memory and a set of 32 GPRs. It also provides for word and dou-
ble-word operand loads and stores between memory and a set of 32 floating-point
registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a com-
putation and then modify the same or another memory location, the memory contents
must be loaded into a register, modified, and then written back to the target location with
distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution
state. However, the flow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of sev-
eral components of the system software to be invoked.
CALCULATING EFFECTIVE ADDRESSES:
The effective address (EA) is the 32-bit
address computed by the processor when executing a memory access or branch
instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
EA = (RA|0) + offset (including offset = 0) (register indirect with immediate index)
EA = (RA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory
accesses. Calculation of the effective address for aligned transfers occurs in a single
clock cycle.
For a memory access instruction, if the sum of the effective address and the operand
length exceeds the maximum effective address, the memory operand is considered to
wrap around from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit
unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
PowerPC 603rMicroprocessor
Instruction Set
The 603r instruction set is defined as follows:
The 603r provides hardware support for all 32-bit PowerPC instructions.
The 603r provides two implementation-specific instructions used for software table
search operations following TLB misses:
- Load Data TLB Entry (
tlbld
)
- Load Instruction TLB Entry (
tlbli
)
The 603r implements the following instructions which are defined as optional by the
PowerPC architecture :
- External Control In Word Indexed (
eciwx
)
- External Control Out Word Indexed (
ecowx
)
- Floating Select (
fsed
)
- Floating Reciprocal Estimate Single-Precision (
fres
)
- Floating Reciprocal Square Root Estimate (
frsqrte
)
- Store Floating-Point as Integer Word (
stfiwx
)
Cache Implementation
The following subsections describe the PowerPC architecture
’
s treatment of cache in
general, and the 603r specific implementation, respectively.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMG10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
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