參數(shù)資料
型號(hào): TSPC603R
英文描述: TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述: TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫
文件頁數(shù): 20/44頁
文件大小: 636K
代理商: TSPC603R
20
TSPC603R
2125A
HIREL
04/02
5. t
sysclk
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multi-
plied by the period of SYSCLK to compute the actual time duration (ns) of the parameter in question.
6. Output signal transitions from GND to 2.0V or V
DD
to 0.8V.
7. Nominal precharge width for ABB and DBB is 0.5 * t
sysclk
.
8. Nominal precharge width for ARTRY is 1.0 * t
sysclk
.
Figure 8.
Output Timing Diagram
JTAG AC Timing
Specifications
SYSCLK
12
14
13
15
16
TS
ARTRY
ABB, DBB
VM
VM
VM = Midpoint V
oltage (1.4V)
VM
13
20
18
17
21
19
15
16
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY)
Table 14.
JTAG AC Timing Specifications (independent of SYSCLK)
V
DD
= A
V
DD
= 2.5V
±
5%; O
V
DD
= 3.3
±
5%V, GND = 0V, C
L
= 50 pF, -55
°
C
T
C
125
°
C
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
ns
2
TCK clock pulse width measured at 1.4V
25
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
ns
1
5
TRST assert time
40
ns
6
Boundary scan input data setup time
6
ns
2
7
Boundary scan input data hold time
27
ns
2
8
TCK to output data valid
4
25
ns
3
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