參數(shù)資料
型號(hào)： TSPC603R
英文描述： TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述： TSPC603R [更新4 / 02。 44頁(yè)] 32位RISC微處理器。 166-300兆赫
文件頁(yè)數(shù)： 34/44頁(yè)
文件大?。?/td> 636K
代理商： TSPC603R
34
TSPC603R
2125A
–
HIREL
–
04/02
Memory Management
The following subsections describe the memory management features of the PowerPC
architecture, and the 603r implementation, respectively.
PowerPC Memory
Management
The primary functions of the MMU are to translate logical (effective) addresses to physi-
cal addresses for memory accesses, and to provide access protection on blocks and
pages of memory.
There are two types of accesses generated by the 603r that require address
translation
—
instruction accesses, and data accesses to memory generated by load
and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Vir-
tual memory management permits execution of programs larger than the size of
physical memory; demand-paged implies that individual pages are loaded into physical
memory from system memory only when they are first accessed by an executing
program.
The hashed page table is a variable-sized data structure that defines the mapping
between virtual page numbers and physical page numbers. The page table size is a
power of 2, and its starting address is a multiple of its size.
The page table contains a number of page table entry groups (PTEGs). A PTEG con-
tains eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is
64 bytes long. PTEG addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
PowerPC 603rMicroprocessor
Memory Management
The instruction and data memory management units in the 603r provide 4-Gbyte of logi-
cal address space accessible to supervisor and user programs with a 4-Kbyte page size
and 256M byte segment size. Block sizes range from 128-Kbyte to 256-Mbyte and are
software selectable. In addition, the 603r uses an interim 52-bit virtual address and
hashed page tables for generating 32-bit physical addresses. The MMUs in the 603r rely
on the exception processing mechanism for the implementation of the paged virtual
memory environment and for enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of
the most recently used page table entries. Software is responsible for maintaining the
consistency of the TLB with memory. The 603r
’
s TLBs are 64-entry, two-way set-asso-
ciative caches that contain instruction and data address translations. The 603r provides
hardware assist for software table search operations through the ashed page table on
TLB misses. Supervisor software can invalidate TLB entries selectively.
The 603r also provides independent four-entry BAT arrays for instructions and data that
maintain address translations for blocks of memory. These entries define blocks that
can vary from 128-Kbyte to 256-Mbyte. The BAT arrays are maintained by system
software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized
data structure that defines the mapping between virtual page numbers and physical
page numbers. The page table size is a power of 2, and its starting address is a multiple
of its size.
Also as specified by the PowerPC architecture, the page table contains a number of
page table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of
eight bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry
points for table search operations.
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參數(shù)描述
TSPC603RCAB/Q8L 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RCAB/Q8LC 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8L 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8LC 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMG10LC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
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