參數(shù)資料
型號(hào)： TSPC603R
英文描述： TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述： TSPC603R [更新4 / 02。 44頁(yè)] 32位RISC微處理器。 166-300兆赫
文件頁(yè)數(shù)： 30/44頁(yè)
文件大小： 636K
代理商： TSPC603R
30
TSPC603R
2125A
–
HIREL
–
04/02
Cache coherency is enforced by on-chip bus snooping logic. Since the 603r
’
s data
cache tags are single ported, a simultaneous load or store and snoop access represent
a resource contention. The snoop access is given first access to the tags. The load or
store then occurs on the clock following snoop.
Figure 14.
Data Cache Organization
Exception Model
The following subsections describe the PowerPC exception model and the 603r imple-
mentation, respectively.
PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state
as a result of external singles, errors, or unusual conditions arising in the execution of
instructions, and differ from the arithmetic exceptions defined by the IEEE for float-
ing-point operations. When exceptions occur, information about the state of the
processor is saved to certain registers and the processor begins execution at an
address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the
exception - for example, the DSISR and the FPSCR. Additionally, some exception con-
ditions can be explicitly enable or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; there-
fore, although a particular implementation may recognize exception conditions out of
order, they are presented strictly in order. When an instruction-caused exception is rec-
ognized, any unexecuted instructions that appear earlier in the instruction stream,
including any that have not yet entered the execute state, are required to complete
before the exception is taken. Any exceptions caused by those instructions are handled
first. Likewise, exceptions that are asynchronous and precise are recognized when they
occur, but are not handled until the instruction currently in the completion state success-
fully completes execution or generates an exception, and the completed store queue is
emptied.
Unless a catastrophic event causes a system reset or machine check exception, only
one exception is handled at a time. If, for example, a single instruction encounters multi-
ple exception conditions, those conditions are encountered sequentially.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSPC603RCAB/Q8L 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RCAB/Q8LC 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8L 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMAB/Q8LC 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e
TSPC603RMG10LC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
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