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| 型號(hào)： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 29/44頁 |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
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TSPC603R
2125A
–
HIREL
–
04/02
PowerPC Cache
Characteristics
The PowerPC architecture does not define hardware aspects of cache implementations.
For example, some PowerPC processors, including the 603r, have separate instruction
and data caches (hardware architecture), while others, such as the PowerPC 601
microprocessor, implement a unified cache.
PowerPC microprocessor controls the following memory access modes on a page or
block basis:
Write-back/write-through mode.
Cache-inhibited mode.
Memory coherency.
Note that in the 603r, a cache line is defined as eight words. The VEA defines cache
management instructions that provide a means by which the application programmer
can affect the cache contents.
PowerPC 603rMicroprocessor
Cache Implementation
The 603r has two 16-Kbyte, four-way set-associative (instruction and data) caches. The
caches are physically addressed, and the data cache can operate in either write-back or
write-through mode as specified by the PowerPC architecture.
The data cache is configured as 128 sets of 4 lines each. Each line consists of 32 bytes,
two state bits, and an address tag. The two state bits implement the three-state MEI
(modified/exclusive/invalid) protocol. Each line contains eight 32-bit words. Note that the
PowerPC architecture defines the term block as the cacheable unit. For the 603r, the
block size is equivalent to a cache line. A block diagram of the data cache organization
is shown in Figure 14.
The instruction cache also consists of 128 sets of 4 lines, and each line consists of
32 bytes, an address tag, and a valid bit. The instruction cache may not be written to
except through a line fill operation. The instruction cache is not snooped, and cache
coherency must be maintained by software. A fast hardware invalidation capability is
provided to support cache maintenance. The organization of the instruction cache is
very similar to the data cache shown in Figure 14.
Each cache line contains eight contiguous words from memory that are loaded from an
8-word boundary (that is, bits A27-A32 of the effective addresses are zero); thus, a
cache line never crosses a page boundary. Misaligned accesses across a page bound-
ary can incur a performance penalty.
The 603
’
s cache lines are loaded in four beats of 64 bits each. The burst load is per-
formed as
“
critical double word first
”
. The cache that is being loaded is blocked to
internal accesses until the load completes. The critical double word is simultaneously
written to the cache and forwarded to the requesting unit, thus minimizing stalls due to
load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device)
implementation, the 603r implemements the MEI protocol. These three states, modified,
exclusive, and invalid, indicate the state of the cache block as follows:
Modified
- The cache line is modified with respect to system memory; that is, data
for this address is valid only in the cache and not in system memory.
Exclusive
- This cache line holds valid data that is identical to the data at this
address in system memory. No other cache has this data.
Invalid
- This cache line does not hold valid data.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMG10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
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