參數(shù)資料
型號(hào)： TSPC603R
英文描述： TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述： TSPC603R [更新4 / 02。 44頁(yè)] 32位RISC微處理器。 166-300兆赫
文件頁(yè)數(shù)： 40/44頁(yè)
文件大?。?/td> 636K
代理商： TSPC603R
40
TSPC603R
2125A
–
HIREL
–
04/02
System Design
Information
PLL Power Supply Filtering
The A
V
DD
power signal is provided on the 603e to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the
A
V
DD
input signal should be filtered using a circuit similar to the one shown in Figure 17.
The circuit should be placed as close to the A
V
DD
pin to ensure it filters out as much
noise as possible. The 0.1 μF capacitor should be closest to the A
V
DD
pin, followed by
the 10 μF capacitor, and finally the 10
resistor to
V
DD
. These traces should be kept
short and direct.
Figure 17.
PLL Power Supply Filter Circuit
Decoupling
Recommendations
Due to the 603e
’
s dynamic power management feature, large address and data buses,
and high operating frequencies, the 603e can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This
noise must be prevented from reaching other components in the 603e system, and the
603e itself requires a clean, tightly regulated source of power. Therefore, it is recom-
mended that the system designer place at least one decoupling capacitor at each
V
DD
and O
V
DD
pin of the 603e. It is also recommended that these decoupling capacitors
receive their power from separate
V
DD
, O
V
DD
, and GND power planes in the PCB, utiliz-
ing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10 μF to provide both high-and
low-frequency filtering, and should be placed as close as possible to their associated
V
DD
or O
V
DD
pin. Suggested values for the
V
DD
pins 220 pF (ceramic), 0.01 μF (ceramic)
and 0.1 μf (ceramic). Suggested values for the O
V
DD
pins 0.01 μF (ceramic), 0.1 μF
(ceramic), and 10 μF (tantalum). Only SMT (surface mount technology) capacitors
should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the
V
DD
and O
V
DD
planes, to enable quick recharging of the
smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent
series resistance) rating to ensure the quick response time necessary. They should also
be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors 100 μF (AVX TPS tantalum) or 330 μf (AVX TPS tantalum).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an
appropriate signal level. Unused active low inputs should be tied to
V
DD
. Unused active
high inputs should be connected to GND. ALL NC (no-connect) signals must remain
unconnected.
Power and ground connections must be made to all external
V
DD
, O
V
DD
, and GND pins
of the 603e.
Vdd
AVdd
0.1
μ
F
10
μ
F
GND
10
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