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參數(shù)資料
| 型號： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 27/44頁 |
| 文件大?。?/td> | 636K |
| 代理商： | TSPC603R |
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TSPC603R
2125A
–
HIREL
–
04/02
Instruction Set and
Addressing Modes
The following subsections describe the PowerPC instruction set and addressing modes
in general.
PowerPC Instruction Set and
Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction for-
mats are consistent among all instruction types, permitting efficient decoding to occur in
parallel with operand accesses. This fixed instruction length and consistent format
greatly simplifies instruction pipelining.
PowerPC Instruction Set:
The PowerPC instructions are divided into the following
categories:
Integer instructions
- These include computational and logical instructions.
- Integer arithmetic instructions
- Integer compare instructions
- Integer logical instructions
- Integer rotate and shift instructions
Floating-point instructions
-These include floating-point computational
instructions, as well as instructions that affect the FPSCR
- Floating-point arithmetic instructions
- Floating-point multiply/add instructions
- Floating-point rounding and conversion instructions
- Floating-point compare instructions
- Floating-point status and control instructions
Load/store instructions
- These include integer and floating-point load and store
instructions
- Integer load and store instruction
- Integer load and store multiple instructions
- Floating-point load and store
- Primitives used to construct atomic memory operations (
lwarx
and
stwcx.
instructions)
Flow control instructions
- These include branching instructions, condition
register logical instructions, trap instructions, and other instructions that affect the
instruction flow
- Branch and trap instructions
- Condition register logical instructions
Processor control instructions
- These instructions are used for synchronizing
memory accesses and management of caches, TLBs, and the segment registers
- Move to/from SPR instructions
- Move to/from MSR
- Synchronize
- Instruction synchronize
Memory control instruction
- These instructions provide control of caches, TLBs,
and segment registers
- Supervisor-level cache management instructions
- User-level cache instructions
- Segment register manipulation instructions
- Translation look aside buffer management instructions
Note that this grouping of the instructions does not indicate which execution unit exe-
cutes a particular instruction or group of instructions.
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相關代理商/技術(shù)參數(shù) |
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| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMG10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
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