
VIA Technologies, Inc.
P
IN
D
ESCRIPTIONS
Preliminary VT6516 Datarsheet
-
14-
No.
Name
Type
Description
SDRAM Interface
SDRAM Data:
64-bit SDRAM data bus. These signals connect directly to the data
input/output pins of the SDRAM devices.
SDRAM Address Bus:
12-bit SDRAM data bus. These signals connect directly to the address
input of the SDRAM devices.
Bank Identifier for Bank 0 and 1:
See Ball
Table
MD[63:0]
I/O
See Ball
Table
MA[11:0]
O
See Ball
Table
BA[1:0]
O
See Ball
Table
RAS
[1:0]
O
Row Address Strobes for Bank 0 and 1:
DRAM row address strobes.
RAS
[0] is used for Bank 0.
RAS
[1] is used
for Bank 1.
Column Address Strobes for Bank 0 and 1:
DRAM column address strobes.
CAS
[0] is used for Bank 0.
CAS
[1] is
used for Bank 1.
DRAM Write Enable for Bank 0 and 1:
See Ball
Table
CAS
[1:0]
O
See Ball
Table
DWE
[1:0]
O
See Ball
Table
DCS
[3:0]
O
DRAM Chip Select:
VT-3061A supports at most 4 SDRAM DIMM modules.
SRAM Interface
SRAM Data:
32-bit SRAM data bus. These signals connect directly to the data
input/output pins of the SRAM devices.
SRAM Address Bus:
18-bit SDRAM data bus. These signals connect directly to the address
input of the SDRAM devices.
SRAM Chip Select:
SRAM Type
Chip Select Pins
----------------
----------------------
32KBx32
SCS[0] & SA[15]
64KBx32
SCS[0] & SA[16]
128KBx32
SCS[0] & SA[17]
256KBx32
SCS[0]
Synchronous Processor Address Status
See Ball
Table
SD[31:0]
I/O
See Ball
Table
SA[17:0]
O
See Ball
Table
SCS
[4:0]
O
Address Pins
------------------
SA[14:0]
SA[15:0]
SA[16:0]
SA[17:0]
See Ball
Table
SADS
[1:0]
O
See Ball
Table
SOE
[1:0]
O
Output Enable
See Ball
Table
SWE
[1:0]
O
SRAM Write Enable:
Miscellaneous Interface