
VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
44-
5000H
MAC & I/O Control Module of Port
11
MAC & I/O Control Module of Port
12
MAC & I/O Control Module of Port
13
MAC & I/O Control Module of Port
14
MAC & I/O Control Module of Port
15
CPU IO Control Module
CPU packet read byte count register bits
[7:0]
CPU packet read byte count register bits
[10:8]
CPU packet read status register
as same as Port 0
5400H
as same as Port 0
5800H
as same as Port 0
5C00H
as same as Port 0
6000H
as same as Port 0
6400H
00H
PKT_BYTE_C
NT
PKT_BYTE_C
NT
RD_PKT_STA
TUS
PKT_SRC_PO
RT
CPUIO_CFG
[7:0] 0
R/O
01H
[10:8
]
[1:0] 0
0
R/O
02H
R/O
03H
Packet source port ID
[3:0] 0
R/O
04H
CPU IO port configuration register
[1:0] 0
R/
W
R/O
10H
CPU packet write status register
WR_PKT_STA
TUS
[2:0] 0
4. D
ETAIL OF
S
WITCH
R
EGISTER
4.1 Registers of SDRAM Control Module
* Base Address: 0000H
Addres
s
(offset
)
00H
SDRAM TYPE:
0: 16Mbit SDRAM chip (default)
1: 64Mbit
Function
Register
Name
Bits
Defau
lt
Value
R/
W
This register has to be specified before initialization of the buffer
control because the Bank 1 free buffer pointer should have initial
value 130 for 16Mbit SDRAM, or, initial value 131 for 64Mbit
SDRAM.
CAS Latency for read operation:
2’b00: latency 1
2’b01: latency 2
2’b10: latency 3 (default)
SDRAMTYPE [0]
0
R/W
01H
This latency specifies the required delay between the CAS cycle and
the first read cycle. Note that the CAS latency has to be specified
before using RSDM in SDRAM initialization.
CL
[1:0]
2
R/W