
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
3
T
ABLE OF
C
ONTENTS
T
ABLE OF
C
ONTENTS
................................................................................................................................3
F
IGURES AND
T
ABLES
...............................................................................................................................4
R
EVERSION
H
ISTORY
................................................................................................................................5
F
EATURES
................................................................................................................................................6
B
LOCK
D
IAGRAM
......................................................................................................................................9
B
ALL OUT
D
IAGRAM
............................................................................................................................... 11
RMII-mode Ball out Diagram ........................................................................................................... 11
MII-mode Ballout Diagram............................................................................................................... 12
L
OGIC
S
YMBOL
...................................................................................................................................... 13
P
IN
D
ESCRIPTIONS
.................................................................................................................................. 14
J
UMPER
S
TRAPPING
................................................................................................................................. 18
SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 19
1. G
ENERAL
D
ESCRIPTION
...................................................................................................................... 19
2. T
HE
VIA E
THER
S
WITCH
A
RCHITECTURE
............................................................................................ 19
2.1 Switch initialization procedures.................................................................................................. 19
2.2 Packet receiving and forwarding follow.......................................
3. I
NTERFACE
D
ESCRIPTIONS
................................................................................................................... 20
3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..
4. F
UNCTIONAL
D
ESCRIPTION
................................................................................................................. 33
4.1 Packet Reception and Address recognition.................................................................................. 33
4.2 Packet Forwarding and VLAN..................................................................................................... 33
4.3 Network Management Features................................................................................................... 34
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SECTION II REGISTER MAP............................................................................................................... 36
1. R
EGISTER
T
ABLES
............................................................................................................................. 36
2 CPU I
NTERFACE
R
EGISTERS
M
AP
......................................................................................................... 36
3 S
WITCH
I
NTERNAL
R
EGISTERS
M
AP
..................................................................................................... 37
4. D
ETAIL OF
S
WITCH
R
EGISTER
.............................................................................................................. 44
4.1 Registers of SDRAM Control Module......................................................................................... 44
4.2 Registers of SRAM Control Module............................................................................................ 46
4.4 Registers of Buffer Control Module............................................................................................. 48
4.5 Registers of Forwarding Control Module................................................................................... 49
4.6 Registers of PHY Control Module.............................................................................................. 53
4.7 Registers of EEPROM Control Module....................................................................................... 55
4.8 Registers of CPU Interface Module............................................................................................. 56
4.9 Registers of MAC/IO Control Module......................................................................................... 59
4.10 Registers of CPU IO Control Module....................................................................................... 63
SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 65
A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................... 65
DC C
HARACTERISTICS
............................................................................................................................ 65
AC C
HARACTERISTICS
............................................................................................................................ 65
P
ACKAGE
M
ECHANICAL
S
PECIFICATIONS
................................................................................................. 73