
VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
56-
Addres
s
(offset
)
00H
Function
Register
Name
Bits
Defau
lt
Value
R/
W
EEPROM word address
For a 256-byte EEPROM device, an 8-bit data object is identified
with this register. For a 512-byte EEPROM device, an 8-bit data
object is identified with this register plus EEDEVADDR[1]. For a
1024-byte EEPROM device, an 8-bit data object is identified with
this register plus EEDEVADDR[2:1], vice versa.
EEPROM data
EEWDAD
DR
[7:0]
W/
O
01H
Every data access to EEPROM is in unit of 8 bits, stored in this
register.
EEPROM device address
bit 7-4 : device type id (EEPROM 1010)
bit 3-1 : device id
bit 0 : r/w command , value 0: write; value 1: read
EEDATA [7:0]
R/
W
02H
The triple of 4-bit PHY device type ID, 3-bit device ID, and 7-bit
word address forms a unique access address to an 8-bit EEPROM
data object.
This register’s bit 0 is used to specify the command type: 0 for write
and 1 for read. A read or write operation takes about 0.4 ms so that
the CPU has to read the EEYSTS register periodically to check if the
issued command is “complete without error” or “ack error”.
EEPROM status register
3’b000: idle
3’b001: busy
3’b010: complete without error
3’b100: ack error
EEDEVA
DDR
[7:0]
W/
O
03H
This register indicates the status of the EEPROM control module.
Initially, the EEPROM control module is in the idle status. While a
read or write command is issued by writing 1/0 to EEDEVADDR[0],
EESTS becomes “busy” immediately, and goes into the “complete”
status as this operation finishes or into the “ack error” as an
acknowledge error happens. Then, a following “read status”
command will cause it back to the “idle” status, or a following
read/write command will cause it into the “busy” status.
EESTS
[2:0]
R/O
4.8 Registers of CPU Interface Module
* Base Address: 2000H
Addres
s
(offset
)
Function
Register
Name
Bits
Defau
lt
Value
R/
W