VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
63-
20H-
23H
sent bad packet counter
Formal Definition: "The number of outbound
packets that could not be transmitted because of
errors."
Accounting Event: re-transmission due to collision
or output FIFO underrun.
2800H MAC & I/O Control Module of Port 1
2C00
H
3000H MAC & I/O Control Module of Port 3
3400H MAC & I/O Control Module of Port 4
3800H MAC & I/O Control Module of Port 5
3C00
H
4000H MAC & I/O Control Module of Port 7
4400H MAC & I/O Control Module of Port 8
4800H MAC & I/O Control Module of Port 9
4C00
H
5000H MAC & I/O Control Module of Port 11
5400H MAC & I/O Control Module of Port 12
5800H MAC & I/O Control Module of Port 13
5C00
H
6000H MAC & I/O Control Module of Port 15
XMT_BA
D_PKT
[31:0
]
0
R/O
as same as Port 0
as same as Port 0
MAC & I/O Control Module of Port 2
as same as Port 0
as same as Port 0
as same as Port 0
as same as Port 0
MAC & I/O Control Module of Port 6
as same as Port 0
as same as Port 0
as same as Port 0
as same as Port 0
MAC & I/O Control Module of Port 10
as same as Port 0
as same as Port 0
as same as Port 0
as same as Port 0
MAC & I/O Control Module of Port 14
as same as Port 0
4.10 Registers of CPU IO Control Module
* Base Address: 6400H
Addres
s
(offset
)
00H
CPU packet read byte count register bits [7:0]
Function
Register
Name
Bits
Defau
lt
Value
R/
W
CPU can check the incoming packet length VIA the 11-bit register
PKT_BYTE_CNT [10:0] before starting to read it.
CPU packet read byte count register bits [10:8]
PKT_BYT
E_CNT
[7:0]
0
R/O
01H
PKT_BYT
E_CNT
[10:8
]
0
R/O