參數(shù)資料
型號: VT6516
廠商: Electronic Theatre Controls, Inc.
英文描述: 16/12 PORT 10/1000 ASE T/TX
中文描述: 16/12港口10/1000日月光噸/德克薩斯州
文件頁數(shù): 64/73頁
文件大?。?/td> 440K
代理商: VT6516
VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
64-
02H
CPU packet read status register
2’b00: idle or packet read in progress
2’b01: packet received successfully
2’b10: packet received with error
(CPU needs to read the same packet again)
Packet source port ID
RD_PKT_
STATUS
[1:0] 0
R/O
03H
CPU can check the incoming packet’s source port
ID VIA the 3-bit register PKT_SRC_PORT before
starting to read it. It is useful to the spanning tree
algorithm.
CPU IO port configuration register
bit 0 : input port enable , 1: input enable, 0: input disable
bit 1 : output port enable , 1: output enable, 0: output disable
CPU packet write status register
bits [1:0] : packet write status
2’b00: idle or packet write in progress
2’b01: CPU sent packet successfully
2’b10: CPU sent packet unsuccessfully
(CPU needs to re-write the packet again)
bit 2: CPU Input Control is ready for CPU to write packets
(It can be ready only after setting CPUIO_CFG[0] = 1.)
0: not ready (default)
1: ready
PKT_SRC
_PORT
[3:0] 0
R/O
04H
CPUIO_C
FG
WR_PKT_
STATUS
[1:0] 0
R/
W
R/O
10H
[2:0] 0
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