
VIA Technologies, Inc.
Preliminary VT6516 Datasheet
4
F
IGURES AND
T
ABLES
Figure 1: Block Diagram.............................................................................................9
Figure 3-3 .................................................................................................................22
Figure 3-6: Algorithm of Initialization of Free Link Lists...........................................22
Figure 3-1 SRAM......................................................................................................26
Figure 3-2 Free buffer link structure..........................................................................27
Table 1-0 Free buffer link structure............................................................................27
Figure 3-5 The Address table entries structure +........................................................27
Table 1-1 Address table structure..............................................................................28
Table 3-1 RMII interface signals................................................................................30
Figure 3-1 RMII timing diagram................................................................................30
Table 3-2 MII interface signals..................................................................................31
Figure 3-2 MII timing diagram ..................................................................................31