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參數(shù)資料
| 型號(hào)： | VT6516 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16/12 PORT 10/1000 ASE T/TX |
| 中文描述： | 16/12港口10/1000日月光噸/德克薩斯州 |
| 文件頁數(shù)： | 45/73頁 |
| 文件大?。?/td> | 440K |
| 代理商： | VT6516 |
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VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
45-
02H
SDRAM Operation Mode:
For the bits [2:0], the operation modes are defined as follows:
3’b000: Normal SDRAM Mode
3’b001: NOP Command Enable
3’b010: Precharge All Banks
3’b011: MSR Enable (Mode Register Set Enable)
3’b100: CBR Refresh Cycle Enable
others: idle for power-up
For the bit [3], it is called REFRESH_EN, defined as follows:
0: turn off hardware refresh cycle (default)
1: turn on hardware refresh cycle
After the last refresh operation issued by software in the
initialization cycle, software should enable the bit “REFRESH_EN”
immediately to notify SDRAM control module ‘sdramctl’ to start
generating refresh cycle periodically.
The initialization of SDRAM control module is illustrated as
follows:
SDRAMTYPE
0 : 16Mb
CL
1 : read latency = 2
(3) delay 1 s
(4) RSDM
1 : NOP
(5) delay 1 s
(6) RSDM
2 : Precharge
(7) delay 1 s
(8) loop 7 times
RSDM
4 : Refresh
delay 1 s
RSDM
1 : NOP
delay 1 s
(9) RSDM
0CH : Refresh & turn on hardware refresh
(10) delay 1 s
(11) RSDM
0BH : Mode Register Set Enable
(12) delay 1 s
(13) RSDM
08H : Normal SDRAM Mode
(14) END0A
0x04 : DIM bank 0 ending address = 32MB
(15) END1A
0x08 : DIM bank 1 ending address = 64MB
(16) END2A
0x0C : DIM bank 2 ending address = 96MB
(17) END3A
0x10 : DIM bank 3 ending address = 128MB
Bits [27:23] of DIMM Bank 0 Ending Address
RSDM
[3:0]
5
R/W
03H
For the case that there are two 32MB SDRAM modules plugged in
DIMM slot 0 and two 16MB SDRAM modules plugged in DIMM
slot 1, assign the registers as follows
END0A = 04H to indicate the ending address of DIMM Bank 0 is at
2^25 (32MB)
END1A = 08H to indicate the ending address of DIMM Bank 1 is at
2^26 (64MB)
END2A = 0AH to indicate the ending address of DIMM Bank 0 is at
2^26+2^24 (80MB)
END3A = 0CH to indicate the ending address of DIMM Bank 0 is at
2^26+2^25 (96MB)
Bits [27:23] of DIMM Bank 1 Ending Address
(see END0A)
Bits [27:23] of DIMM Bank 2 Ending Address
(see END0A)
Bits [27:23] of DIMM Bank 3 Ending Address
(see END0A)
END0A
[4:0]
0
R/W
04H
END1A
[4:0]
0
R/W
05H
END2A
[4:0]
0
R/W
06H
END3A
[4:0]
0
R/W
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