VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
18-
RMII interface
See Ball
Table
See Ball
Table
See Ball
Table
See Ball
Table
See Ball
Table
See Ball
Table
CRS_DV[15:0
]
RXD0[15:0]
I
Carries sense and data valid from port 15 to port 0 :
I
Receive data zero from port 15 to port 0 :
RXD1[15:0]
I
Receive data one from port 15 to port 0 :
TXEN[15:0]
O
Transmit enable from port 15 to port 0 :
TXD0[15:0]
O
Transmit data zero from port 15 to port 0 :
TXD1[15:0]
O
Transmit data one from port 15 to port 0 :
Power Supply & Ground
See Ball
Table
See Ball
Table
VDD, VDDA
P
Positive 3.3V Supply: Supply power to Internal digital logic, Digital I/O
pads, and TD, TX pads. Double bonding may be required.
Negative Supply: digital ground. Multiple bonding pads are required to
separate core and I/O pads ground.
VSS, VSSA
G
J
UMPER
S
TRAPPING
Jumper
HOST Clock
J1 [5-6], [3-4], [1-
2]
Pin
Description
SYSLED[3:
1]
HOST Clock (HCLK) Rate Selection:
J1[OFF,OFF,OFF] (SYSLED[3:1]==3’b111)
J1[ OFF,OFF, ON] (SYSLED[3:1]==3’b110)
J1[OFF, ON, OFF] (SYSLED[3:1]==3’b101)
J1[OFF, ON, ON] (SYSLED[3:1]==3’b100)
J1[ ON,OFF,OFF] (SYSLED[3:1]==3’b011)
=> 8MHz
=> 16MHz
=> 25MHz
=> 4MHz
=> 33MHz
PHY Mode
J1 [7-8]
SYSLED[4] PHY Device Selection:
J1[OFF] (SYSLED[4]==1’b1)
J1[ ON] (SYSLED[3:1]==1’b0)
=> RMII PHY
=> MII PHY
SRAM Type
J1 [11-12,9-10]
SYSLED[6:
5]
SRAM Device Type Selection:
J1[OFF,OFF] (SYSLED[6:5]==2’b11)
J1[OFF,ON] (SYSLED[6:5]==2’b10)
J1[ON,OFF] (SYSLED[6:5]==2’b01)
=> 64K x 32 SRAM
=> 128K x 32 SRAM
=> 32K x 32 SRAM