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參數(shù)資料
| 型號(hào)： | VT6516 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16/12 PORT 10/1000 ASE T/TX |
| 中文描述： | 16/12港口10/1000日月光噸/德克薩斯州 |
| 文件頁(yè)數(shù)： | 54/73頁(yè) |
| 文件大小： | 440K |
| 代理商： | VT6516 |
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VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-
54-
Addres
s
(offset
)
00H
Function
Register
Name
Bits
Defau
lt
Value
R/
W
PHY ID
This is used to specify which PHY device is the objective of the
following MII commands. There are maximum 16 RMII PHY
devices.
PHY register address
PHYID
[3:0] 0
W/
O
01H
In each PHY device, there are maximum 32 MII management
registers accessible by the CPU. The PHY_REG_ADDR register is
used to specify which one is the objective of the following access
command.
PHY data register
PHY_REG
_ADDR
[4:0] 0
W/
O
02-
03H
Each PHY management register is 16 bits. Every data access to a
PHY management register is in unit of 16 bits, stored in this
register.
PHY command register
1: read
0: write
PHYDAT
A
[15:0
]
R/
W
04H
Write 0 to this register will cause a write operation to the PHY
management register (specified by the PHY_REG_ADDR) of the
PHY device (specified by the PHYID). Write 1 to this register will
cause a read operation. A read or write operation takes about 0.4 ms
so that the CPU has to read the PHYSTS register periodically to
check if the issued command is complete.
PHY status register
2’b00: idle
2’b01: busy
2’b10: complete
PHYCMD [0]
W/
O
05H
This register indicates the status of the PHY control module.
Initially, the PHY control module is in the idle status. While a read
or write command is issued by writing 1/0 to the PHYCMD register,
PHYSTS becomes “busy” immediately, and goes into the
“complete” status as this operation finishes. Then, a following “read
status” command will cause it back to the “idle” status, or a
following read/write command will cause it into the “busy” status.
PORT0 PHY Device Address
PHYSTS
[1:0] 0
R/O
10H
The pair of 5-bit PHY device address and 5-bit register address
forms a unique access address to a PHY device’s register. Each PHY
device has a unique device address that is identified by the PHYID.
In the system initialization, the CPU should write PHY device
addresses, corresponding to every PHY devices, to registers
PORT[0..15]_PHY_ADDR, that may be recorded in the EEPROM
or code ROM.
PORT1 PHY Device Address
PORT0_P
HY_ADD
R
[4:0] 0
R/
W
11H
PORT1_P
HY_ADD
R
PORT2_P
HY_ADD
R
[4:0] 0
R/
W
12H
PORT2 PHY Device Address
[4:0] 0
R/
W
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