參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 101/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
á
PRELIMINARY
DS3 ATM UNI/CLEAR CHANNEL FRAMER IC
XRT72L71
REV. P1.0.5
101
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
Figure 1. XRT72L71 Simplified Block Diagram with System Interfaces ........................................................... 1
Figure 2. Block Diagram of the XRT72L71 DS3 UNI ........................................................................................ 2
SYSTEM/FUNCTIONAL DESCRIPTION ............................................................................ 3
FUNCTIONAL DESCRIPTION ............................................................................................ 3
THE ATM UNI MODE OF OPERATION ........................................................................... 3
The Receive Section ....................................................................................................... 3
The Transmit Section ..................................................................................................... 4
Clear-channel-framing Mode of operation .................................................................... 5
THE RECEIVE SECTION ........................................................................................................................................5
THE TRANSMIT SECTION......................................................................................................................................5
The Microprocessor Interface Section .......................................................................... 6
Performance Monitor Section ........................................................................................ 6
Test and Diagnostic Section .......................................................................................... 6
FOR ATM UNI APPLICATIONS...............................................................................................................................6
FOR CLEAR-CHANNEL FRAMING APPLICATIONS..............................................................................................6
Line Interface Drive and Scan Section .......................................................................... 7
C
LEAR
C
HANNEL
M
ODE
O
PERATION
............................................................................................................. 7
Features ........................................................................................................................... 8
Transmit and Receive Sections ..................................................................................... 8
UTOPIA Interface Blocks ........................................................................................................................ 8
Transmit Cell Processor Block ................................................................................................................ 9
Receive Cell Processor Block ................................................................................................................. 9
Transmit PLCP Processor Block ............................................................................................................. 9
Receive PLCP Processor Block .............................................................................................................. 9
Transmit/Receive DS3 Framer Block ...................................................................................................... 9
Microprocessor Interface Section ............................................................................................................ 9
Performance Monitor Section ................................................................................................................ 10
Test and Diagnostic Section ................................................................................................................. 10
Line Interface Drive and Scan Section .................................................................................................. 10
Figure 3. Pin Out of the XRT72L71 DS3 ATM UNI ........................................................................................ 11
ORDERING INFORMATION ............................................................................................. 11
PIN DESCRIPTION ........................................................................................................ 12
ABSOLUTE MAXIMUM RATINGS ................................................................................... 31
DC ELECTRICAL CHARACTERISTICS ........................................................................... 31
AC ELECTRICAL CHARACTERISTICS ........................................................................... 31
TIMING DIAGRAMS ...................................................................................................... 37
Figure 4. XRT72L71 Transmit UTOPIA Interface Block Timing ..................................................................... 37
Figure 5. GFC Nibble-Field Serial Input Interface (at Transmit Cell Processor) Timing ................................. 37
Figure 6. Transmit PLCP Processor—POH Byte Serial Input Port Interface Timing ...................................... 38
Figure 7. Transmit DS3 Framer—OH Bit Serial Input Port Interface Timing .................................................. 38
Figure 8. Transmit DS3 Framer Line Interface Output Timing (TxPOS and TxNEG are updated on the rising
edge of TxLineClk) ....................................................................................................................... 39
Figure 9. Transmit DS3 Framer Line Interface Output Timing (TxPOS and TxNEG are updated on the falling
edge of TxLineClk) ....................................................................................................................... 39
Figure 10. Receive DS3 Framer—OH Bit Serial Output Port Interface Timing .............................................. 40
Figure 11. Receive DS3 Framer Line Interface Input Signal Timing (RxPOS and RxNEG are sampled on rising
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