參數(shù)資料
型號(hào)： XRT72L71
廠(chǎng)商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 29/104頁(yè)
文件大?。?/td> 1156K
代理商： XRT72L71
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
PRELIMINARY
REV. P1.0.5
29
146
TxUAddr4
I
Transmit UTOPIA Address Bus—MSB Input:
This input pin, along with
TxUAddr3 through TxUAddr0 comprise the Transmit UTOPIA Address Bus
input pins. The Transmit UTOPIA Address Bus is only in use when the UNI is
operating in the M-PHY mode. When the ATM Layer processor wishes to write
data to a particular UNI device, it will provide the address of the “intended
UNI” on the Transmit UTOPIA Address Bus. The contents of the Transmit
UTOPIA Address Bus input pins are sampled on the rising edge of TxUClk.
The DS3 UNI will compare the data on the Transmit UTOPIA Address Bus with
the pre-programmed contents of the TxUT Address Register (Address = 70h).
If these two values are identical and the TxUEN pin is asserted, then the TxU-
Clav pin will be driven to the appropriate state (based upon the TxFIFO fill
level) for the Cell Level handshake mode of operation.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in either the “Clear-Channel-Framer” Mode or
in the “Single-PHY” Mode.
147
TxUAddr0
I
Transmit UTOPIA Address Bus Input—LSB:
(See Description for TxUAddr4
pin 146).
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in either the “Clear-Channel-Framer” Mode or
in the “Single-PHY” Mode.
148
149
150
TxUAddr3
TxUAddr1
TxUAddr2
I
Transmit UTOPIA Address Bus Input:
Please see description for TxUAddr4, pin 146.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in either the “Clear-Channel-Framer” Mode or
in the “Single-PHY” Mode.
151
TxUClk
I
Transmit UTOPIA Interface Clock:
The Transmit UTOPIA Interface clock is
used to latch the data on the Transmit UTOPIA Data bus, into the Transmit
UTOPIA Interface block. This clock signal is also used as the timing source for
circuitry used to process the ATM cell data into and through the TxFIFO.
During Multi-PHY operation, the data on the Transmit UTOPIA Address bus
pins is sampled on the rising edge of TxUClk.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
152
GND
***
Ground Signal Pin
153
TestMode
***
Factory Test Mode Pin
N
OTE
:
The user should tie this pin to ground.
154
TxGFCMSB
O
Transmit GFC Nibble-Field Serial Input Port—MSB Indicator:
This signal,
along with TxGFC and TxGFCClk combine to function as the “Transmit GFC
Nibble Field” serial input port. This output signal will pulse “High” when the
MSB (most significant bit) of the GFC Nibble (for a given cell) is expected at
the TxGFC input pin.
N
OTE
:
This output pin is only active whenever the XRT72L71 has been con-
figured to operate in the “ATM UNI” Mode.
155
Reset
I
Reset Input:
When this active-”Low” signal is asserted, the UNI Framer will
be asynchronously reset. Additionally, all outputs will be “tri-stated”, and all
on-chip registers will be reset to their default values.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
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