參數(shù)資料
型號(hào)： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 52/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
52
T
ABLE
8:
T
EST
C
ELL
E
RROR
A
CCUMULATOR
H
OLDING
R
EGISTER
R
EGISTER
7 T
EST
C
ELL
E
RROR
A
CCUMULATOR
H
OLDING
R
EGISTER
H
EX
A
DDRESS
: 0
X
07
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HOLDING
REGISTER
RO
0x00
Holds the “Unread” byte of the 16-bit Test Cell Error Accumulator, when that
register is read. The XRT72L71 will transfer the contents of the “Unread”
byte to this “Holding” register, anytime the Bidirectional Data Bus (of the
Microprocessor Interface) is configured to be 8-bits wide.
N
OTE
:
This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
9:
T
EST
C
ELL
H
EADER
B
YTE
-1
R
EGISTER
8 T
EST
C
ELL
H
EADER
B
YTE
-1 H
EX
A
DDRESS
: 0
X
08
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 1
R/W
0x11
Test Cell Header Byte - 1
Permits the user to define the value of “Header Byte # 1” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
10:
T
EST
C
ELL
H
EADER
B
YTE
-2
R
EGISTER
9 T
EST
C
ELL
H
EADER
B
YTE
-2 H
EX
A
DDRESS
: 0
X
09
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 2
R/W
0x22
Test Cell Header Byte - 2
Permits the user to define the value of “Header Byte # 2” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
11:
T
EST
C
ELL
H
EADER
B
YTE
-3
R
EGISTER
10 T
EST
C
ELL
H
EADER
B
YTE
-3 H
EX
A
DDRESS
: 0
X
0A
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 3
R/W
0x33
Test Cell Header Byte - 3
Permits the user to define the value of “Header Byte # 3” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
T
ABLE
12:
T
EST
C
ELL
H
EADER
B
YTE
-4
R
EGISTER
11 T
EST
C
ELL
H
EADER
B
YTE
-4 H
EX
A
DDRESS
: 0
X
0B
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
TEST CELL HEADER
BYTE 4
R/W
0x44
Test Cell Header Byte - 4
Permits the user to define the value of “Header Byte # 4” within each Test Cell
which is generated by the “Test Cell Generator”.
N
OTE
:
This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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XRT72L73 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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