參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 66/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
66
T
ABLE
34:
PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB
R
EGISTER
33 PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB H
EX
A
DDRESS
: 0
X
21
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
LCV Count Low byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - MSB” contains the 16 bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “Low” Byte of this 16-bit expression.
N
OTE
:
This register is only active if the “B3ZS Decoder” (within the
XRT72L71) has been enabled.
T
ABLE
35:
PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- MSB
R
EGISTER
34 PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- MSB H
EX
A
DDRESS
: 0
X
22
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
F Bit Error Count High-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON Framing Bit Error Count
Register - LSB” contains the 16 bit value for the total number of Framing Bit
(e.g., both F and M-bit) errors that have been detected since the last read of
this register. This register contains the “High” byte value of this 16-bit
expression.
T
ABLE
36:
PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- LSB
R
EGISTER
35 PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- LSB H
EX
A
DDRESS
: 0
X
23
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
F Bit Error Count low-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON Framing Bit Error Count
Register - MSB” contains the 16 bit value for the total number of Framing Bit
(e.g., both F and M-bit) errors that have been detected since the last read of
this register. This register contains the “Low” byte value of this 16-bit
expression.
T
ABLE
37:
PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB
R
EGISTER
36 PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB H
EX
A
DDRESS
: 0
X
24
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
P-Bit Error Count High-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON P-Bit Error Count Reg-
ister - LSB” contains the 16 bit value for the total number of P Bit errors that
have been detected since the last read of this register. This register con-
tains the “High” byte value of this 16-bit expression.
相關(guān)PDF資料
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