參數(shù)資料
型號: XRT72L71
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 82/104頁
文件大?。?/td> 1156K
代理商: XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
82
T
ABLE
82:
R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-2
R
EGISTER
81 R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-2 H
EX
A
DDRESS
: 0
X
51
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Pattern 2
R/W
0x00
This register (along with the “Rx Idle Cell Mask 2” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 2.
N
OTES
:
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
T
ABLE
83:
R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-3
R
EGISTER
82 R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-3 H
EX
A
DDRESS
: 0
X
52
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Pattern 3
R/W
0x00
This register (along with the “Rx Idle Cell Mask 3” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 3.
N
OTES
:
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
T
ABLE
84:
R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-4
R
EGISTER
83 R
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-4 H
EX
A
DDRESS
: 0
X
53
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Rx Idle Cell Pattern 4
R/W
0x01
This register (along with the “Rx Idle Cell Mask 1” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 4.
N
OTES
:
1. This register should be set to “0x01” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
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