參數(shù)資料
型號: XRT72L71
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 34/104頁
文件大?。?/td> 1156K
代理商: XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
34
fRxLineClk
Clock frequency of RxLineClk
44.736
MHz
t
42
Period of RxLineClk clock signal
10
ns
Receive PLCP Processor (Serial Output Port)—See Figure 13
t
43
Clock Period of RxPOHClk signal
232
ns
t
44
Delay from rising edge of RxPOHClk
signal to rising edge of RxPOHFrame
signal.
6
1.4
ns
t
45
Delay from rising edge of RxPOHClk
to Data valid at RxPOH output
3
10
ns
t
46
Bit period of data at RxPOH output
signal
232
ns
1 RxPOHClk pulse width
Receive Cell Processor (GFC Serial Output Port)—See Figure 14
t
47
Clock Period of RxGFCClk
232
ns
t
48
Delay from rising edge of RxGFCClk
to rising edge of RxGFCMSB pin.
0.06
1.4
ns
t
49
Pulse width of RxGFCMSB signal
232
ns
t
50
Delay from rising edge of RxGFCMSB
signal to first valid bit at RxGFC.
0
ns
t
51
Delay from rising edge of RxGFCClk
to valid bit at RxGFC.
0.9
2.4
ns
t
52
Pulse width of Bit at RxGFC output.
232
ns
Receive UTOPIA Interface Block -- See Figure 15
t
53
Delay time from rising edge of RxUClk
to Data Valid at RxUData[15:0]
1
9.9
16
ns
t
54
Rx UTOPIA Read Enable setup time
to rising edge of RxUClk
4
ns
t
55
Delay time from rising edge of RxUClk
to valid RxUPrty bit
1
10
16
ns
t
56
Delay time from rising edge of RxUClk
to valid RxUSoC bit
1
9.9
16
ns
t
57
Delay time from Read Enable false to
Data Bus being tri-stated
1
11.5
16
ns
t
58
Delay time from Read Enable false to
RxUPrty bit being tri-stated
1
12
16
ns
t
59
Delay time from Read Enable false to
RxUSoC bit being tri-stated
1
11.5
16
ns
t
60
RxUAddr[4:0] Setup Time to rising
edge of RxUClk
4
ns
t
61
RxUAddr[4:0] Hold Time from rising
edge of RxUClk
1
ns
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: T
A
= 25°C, VDD = 3.3V ± 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NITS
C
ONDITIONS
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