參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 26/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
26
112
TxLineClk
O
Transmit Line Interface Clock:
This clock signal is output to the Line Interface
Unit, along with the TxPOS and TxNEG signals. The purpose of this output
clock signal is to provide the LIU with timing information that it can use to gen-
erate the AMI pulses and deliver them over the transmission medium to the Far-
End Receiver. The user can configure the source of this clock to be either the
RxLineClk (from the Receiver portion of the UNI) or the TxIineClk input. The nom-
inal frequency of this clock signal is 44.736 MHz.
113
VDD
***
Power Supply Pin
114
TxSerData/
TxPOH
I
Transmit Serial Payload Data Input/Transmit PLCP Frame POH Byte
Insertion Serial Input:
The exact functionality of this output pin depends upon whether the
XRT72L71 Framer IC is operating in the Clear Channel or ATM Uni Mode.
Clear Channel Mode:
In clear channel mode, this pin can be used by the external interface to pro-
vide the serial input data (payload and OH) that has to be mapped in outgoing
DS3 frame. If user want to insert OH data on TxSer pin then the user should
configure the XRT72L71 accordingly.
ATM UNI Mode:
This input pin becomes active when the user asserts the TxPOHIns input pin.
When this happens the user will be permitted to serially input their own value
for PLCP POH bytes into the “outbound” PLCP frame. This data will be
clocked into the UNI Framer via the TxPOHClk output signal. This UNI will
also assert the TxPOHMSB output pin when it expects the MSB (Most signifi-
cant bit) of the Z6 Byte (within the PLCP frame).
115
TxAISEn
I
Transmit AIS Pattern input:
When this input pin is pulled “High” then the
Transmit DS3 Framer block will insert the AIS pattern into the DS3 output data
stream.
116
TxPOHIns
I
Transmit PLCP Frame POH Data Insert Enable:
This input can be asserted
to allow the user to input his/her own value for the PLCP POH bytes via the
TxPOH input pin, in each PLCP frame, prior to transmission. If this input pin is
not asserted, then the UNI will generate its own PLCP POH bytes.
N
OTE
:
The user should tie this input pin to “GND” if the XRT72L71 is going to
be configured to operate in either the “Clear-Channel-Framer” Mode or in the
“Direct-Mapped ATM” Mode.
117
TxOHIns
I
Transmit Overhead Data Insert Input:
The function of this pin is the same in both Clear Channel and ATM UNI
Modes of the XRT72L71. This pin is used to indicate if the OH bit should be
taken from the external interface. The OH data on TxOH will be considered by
the only if this pin is "High" during OH positions.
118
TxPOHClk
O
Transmit PLCP Frame POH Byte Insertion Clock:
This pin, along with the
TxPOH and the TxPOHMSB input pins, function as the “Transmit PLCP Frame
POH Byte” serial input port. This output pin functions as a clock output signal
that is used to sample the user’s POH data at the TxPOH input pin. This out-
put pin is always active, independent of the state of the “TxPOHIns” pin.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
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S
YMBOL
T
YPE
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ESCRIPTION
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