參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 95/104頁
文件大小： 1156K
代理商： XRT72L71
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
PRELIMINARY
REV. P1.0.5
95
T
ABLE
115:
L
INE
I
NTERFACE
D
RIVE
R
EGISTER
R
EGISTER
114 L
INE
I
NTERFACE
D
RIVE
R
EGISTER
H
EX
A
DDRESS
: 0
X
72
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
R/W
0
6
Reserved
R/W
0
5
REQB
R/W
0
This “Read/Write” bit-field permits the user to control the state of the “REQB”
Output pin. The “REQB” output pin can be connected to the “REQB” input
pin of the XRT7300 and XRT73L00 device.
0: Sets the “REQB” output pin to “0”. If this output pin is connected to the
“REQB” input pin of the LIU IC, then this setting will enable the “Receive
Equalizer” within the LIU IC.
1: Sets the “REQB” output pin to “1”. If this output pin is connected to the
“REQB” input pin of the LIU IC, then this setting will disable the “Receive
Equalizer” within the LIU IC.
N
OTE
:
For guidelines on when to enable or disable the Receive Equalizer,
within the LIU IC, please consult the XRT7300 or the XRT73L00 Data Sheet.
4
TAOS
R/W
0
This “Read/Write” bit-field permits the user to control the state of the “TAOS”
output pin. The “TAOS” output pin can be connected to the “TAOS” input pin
of the XRT7300 and XRT73L00 devices.
0: Sets the “TAOS” output pin to “0”. If this output pin is connected to the
“TAOS” input of the LIU IC, then this setting will configure the Transmit Sec-
tion of the LIU IC to transmit an “All Ones” pattern.
1: Sets the “TAOS” output pin to “1”. If this output pin is connected to the
“TAOS” input pin of the LIU IC, then this setting will NOT configure the Trans-
mit Section of the LIU IC to transmit an “All Ones” pattern.
3
ENCODIS
R/W
1
This “Read/Write” bit-field permits the user to control the state of the “ENCO-
DIS” output pin. The “ENCODIS” output pin can be connected to both the
“ENCODIS” and “DECODIS” input pins of the XRT7300 device, or the “END-
ECDIS” input pin of the XRT73L00 device.
0: Sets the “ENCODIS” output pin to “0”. If this output pin is connected to
the (ENCODIS and DECODIS) or ENDECDIS input pins of the LIU IC, then
this settting will enable the HDB3/B3ZS Encoder/Decoder blocks within the
LIU IC.
1: Sets the “ENCODIS” output pin to “1”. If this output pin is connected to the
“(ENCODIS and DECODIS) or “ENDECDIS input pins fo the LIU IC, then this
setting will disable the “HDB3/B3ZS Encoder/Decoder blocks within the LIU
IC.
2
Tx Lev
R/W
0
This “Read/Write” bit-field permits the user to control the state of the
“TxLEV” output pin. The “TxLEV” output pin can be connected to the
“TxLEV” input pin of the XRT7300 or the XRT73L00 device.
0: Sets the “TxLEV” output pin to “0”. If this output pin is connected to the
“TxLEV” input pin of the LIU IC, then this setting will enable the “Transmit
Line Build-Out” circuit, within the Transmit Section of the LIU IC.
1: Sets the “TxLEV” output pin to “1”. If this output pin is connected to the
“TxLEV” input of the LIU IC, then this setting will disable the “Transmit Line
Build-Out” circuit, within the Transmit Section of the LIU IC.
N
OTE
:
For guidelines on when to enable or disable the “Transmit Line Build-
Out” circuit, within the LIU IC, please consult either the “XRT7300” or the
“XRT73L00” Data Sheet.
相關(guān)PDF資料
PDF描述
XRT72L73 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT72L74 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT
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