參數(shù)資料
型號(hào)： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 19/104頁(yè)
文件大?。?/td> 1156K
代理商： XRT72L71
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
PRELIMINARY
REV. P1.0.5
19
54
55
56
57
58
RxUData7
RxUData14
RxUData6
RxUData13
RxUData5
O
Receive UTOPIA Data Bus Output:
Please see description of RxUData15, pin 53.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
59
VDD
***
Power Supply Pin
60
61
62
63
64
65
RxUData4
RxUData12
RxUData3
RxUData11
RxUData2
RxUData10
O
Receive UTOPIA Data Bus Output:
Please see description of RxUData15, pin 53.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
66
VDD
***
Power Supply Pin
67
68
69
RxUData9
RxUData1
RxUData8
O
Receive UTOPIA Data Bus Output:
Please see description of RxUData15, pin 53.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
70
RxUData0
O
Receive UTOPIA Data Bus Output - LSB:
Please see description of RxUData15, pin 53.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
71
GND
***
Ground Signal Pin
72
RxUSoC
O
Receive UTOPIA Interface—Start of Cell Indicator:
This output pin allows
the ATM Layer Processor to determine the boundaries or the ATM cells that
are output via the Receive UTOPIA Data bus. The Receive UTOPIA Interface
block will assert this signal when the first byte (or word) of a new cell is
present on the Receive UTOPIA Data Bus; RxUData[15:0].
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
73
RxUAddr4
I
Receive UTOPIA Address Bus input (MSB):
This input pin, along with
RxUAddr3 through RxUAddr0 functions as the Receive UTOPIA Address bus
inputs. These input pins are only active when the UNI is operating in the Multi-
PHY Mode. The Receive UTOPIA Address Bus input is sampled on the rising
edge of the RxUClk signal. The contents of this address bus are compared
with the value stored in the “Rx UT Address Register (Address = 6Ch). If
these two values match, then the UNI will inform the ATM Layer Processor on
whether or not it has any new ATM cells to be read from the RxFIFO; by driv-
ing the RxUClav output to the appropriate level. If these two address values
do not match, then the UNI will not respond to the ATM Layer Processor; and
will keep its RxUClav output signal tri-stated.
N
OTE
:
The user should tie this pin to “GND”, whenever the XRT72L71 has
been configured to operate in the “Clear-Channel-Framer” Mode.
74
RxUPrty
O
Receive UTOPIA Interface—Parity Output pin:
The Receive UTOPIA interface
block will compute the odd-parity of each byte (or word) that will place in the
Receive UTOPIA Data Bus. This odd-parity value will be output on this pin,
while the corresponding byte (or word) is present on the Receive UTOPIA Data
Bus.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
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