參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 47/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
PRELIMINARY
REV. P1.0.5
47
T
ABLE
1: UNI O
PERATING
M
ODE
R
EGISTER
R
EGISTER
0 UNI O
PERATING
M
ODE
R
EGISTER
H
EX
A
DDRESS
: 0
X
00
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Local Loop-back
R/W
0
0: Local Loop-back Mode operation is disabled
1: Local Loop-back Mode operation is enabled. The Transmit stream on TxPOS,
TxNEG pins are looped back into the receive RxPOS, RxNEG pins
6
Cell Loop-back
R/W
0
0: Cell Loop-back Mode operation is disabled
1: Cell Loop-back Mode operation is enabled. Cells from the Receive Cell Pro-
cessor block are written into the Tx FIFO.
N
OTE
:
This bit-field is only active if the XRT72L71 is operating in the ATM UNI
Mode.
5
PLCP Loop-back
R/W
0
0: PLCP Loop-back Mode operation is disabled
1: PLCP Loop-back Mode operation is enabled. PLCP frames are looped from
the Transmit PLCP Processor block into the Receive PLCP Processor Block.
N
OTE
:
This bit-field is only active if the XRT72L71 is operating in the ATM UNI/
PLCP Mode.
4
RESET
R/W
0
0: Normal Operation
1: A “0” to “1” transition causes a reset of the UNI/Framer device.
3
Direct-mapped ATM
R/W
1
0: PLCP Mode is enabled. Transmit and Receive PLCP Processor blocks are
enabled.
1: Direct-Mapped ATM Mode. Transmit and Receive PLCP Processor blocks are
disabled.
N
OTE
:
This bit-field is only active if the XRT72L71 is operating in the ATM UNI
Mode.
2
C-BIT/M13
R/W
0
0: XRT72L71 will support the “DS3/C-Bit Parity” Framing Format.
1: XRT72L71 will support the “DS3/M13” Framing Format.
1
Timing Reference
Select (1)
R/W
1
PLCP block
00: Transmitter timings taken from the Receive PLCP Processor (Loop-Timing).
01: 8 kHz reference signal on 8kRef pin used for stuffing and framing
10: StuffCtl is used for stuffing control, framing is asynchronous on power on
11: Fixed stuffing pattern is used. Framing is asynchronous on power on
Framer block
00: Transmitter timings are taken from the Receive DS3 Framer (Loop-Timing)
01: Framing is asynchronous on power-on, and TxInClk is used as the transmit
clock
10: Transmitter follows external pin (TxFrameRef) framing reference
11: Framin is asynchronous on power-on, and TxInClk is used as the transmit
clock
0
Timing Reference
Select (0)
R/W
1
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