參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 90/104頁
文件大小： 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
90
T
ABLE
106:
T
X
CP I
DLE
C
ELL
P
AYLOAD
R
EGISTER
R
EGISTER
105 T
X
CP I
DLE
C
ELL
P
AYLOAD
R
EGISTER
H
EX
A
DDRESS
: 0
X
69
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Tx Idle Cell Payload
R/W
0x5A
This register contains the value of the payload bytes within each “outbound”
Idle Cell. The contents of this register will be repeated 48 times, when filling
the payload of each “outbound” Idle Cell. pRegister is set to 0x5A when
transmitting standard idle cell pattern.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
T
ABLE
107:
UTOPIA C
ONFIGURATION
R
EGISTER
R
EGISTER
106 UTOPIA C
ONFIGURATION
R
EGISTER
H
EX
A
DDRESS
: 0
X
6A
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-6
Unused
RO
0
5
Handshake Mode
R/W
0
0: Transmit and Receive UTOPIA Interface blocks operate in the Octet-Level
handshake mode
1: Transmit and Receive UTOPIA Interfaces blocks operate in the Cell-Level
handshake mode
N
OTE
:
This bit-field is ignore if the XRT72L71 is configured to operate in the
“Clear-Channel Framer” Mode, or if the chip is configured to operate in the
“Multi-PHY” Mode.
4
M PHY
R/W
1
0: Transmit and Receive UTOPIA Interface block operates in the “Single-
PHY” mode
1: Transmit and Receive UTOPIA Interface block operates in the “Multi-PHY”
mode
N
OTE
:
T
his bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
3
Cell of 52Bytes
R/W
0
0: Transmit and Receive UTOPIA Interface blocks process 53 bytes/cell
when the UTOPIA Data Bus width is set to 8 bits. The Transmit and Receive
UTOPIA Interface blocks process 54 bytes when the UTOPIA Data Bus width
is set to 16 bits.
1: Transmit and Receive UTOPIA Interface blocks process 52 bytes/cell,
independent of the UTOPIA Data Bus width.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
2
Tx FIFO Depth(‘1)
R/W
0
00: Operating Depth of Transmit FIFO is 16 cells
01: Operating Depth of Transmit FIFO is 12 cells
10: Operating Depth of Transmit FIFO is 8 cells
11: Operating Depth of Transmit FIFO is 4 cells
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
1
Tx FIFO Depth(0)
R/W
0
0
UTOPIA Width16
R/W
0
0: Transmit and Receive UTOPIA Data Bus Width is configured to be 8 bits.
1: Transmit and Receive UTOPIA Data Bus Width is configured to be16 bits.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
相關PDF資料
PDF描述
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