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參數(shù)資料
| 型號： | XRT72L71 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 24/104頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | XRT72L71 |
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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
24
102
StuffCtl
I
External PLCP Frame Stuff Control:
This input allows the user to externally
exercise or forego trailer nibble stuffing opportunities by the Transmit PLCP
Processor. PLCP trailer nibble stuff opportunities occur in periods of three
PLCP frames (375μs). The first PLCP frame (first within a “stuff opportunity”
period) will have 13 trailer nibbles appended to it. The second PLCP frame
(second within a “stuff opportunity” period) will have 14 trailer nibbles
appended to it. The third PLCP frame (the location of the stuff opportunity) will
contain 13 trailer nibbles if the StuffCtl input is “Low” and 14 trailer nibbles is
the StuffCtl input is “High”.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
103
TxInClk
I
Transmit DS3 Framer Block—Clock Signal:
The Transmit DS3 Framer can
be configured to use this input signal as the timing reference. If this input pin is
chosen to be the timing reference, then the user must supply a "High" quality
44.736 MHz signal to this input pin. In this configuration, frame generation, by
the Transmit DS3 Framer, will be asynchronous (with any other timing signals
within the UNI). However, frame timing will be based upon this clock signal.
N
OTE
:
This input pin should be tied to “GND” if it is not used as the Transmit
DS3 Framer timing reference.
104
RxPLOF
O
Receive PLCP—“Loss of Frame” Output Indicator:
The Receive PLCP
Processor will assert this pin, when it declares a “Loss of Frame” condition. This
output will be negated when the Receive PLCP Processor reaches the “In
Frame” Condition.
N
OTE
:
This output pin is only active if the user has configured the XRT72L71
to operate in the “ATM UNI” Mode.
105
GND
***
Ground Signal Pin
106
RxPOOF
O
Receive PLCP “Out of Frame” Indicator:
The Receive PLCP Processor will
assert this pin, when it declares an “Out of Frame” condition. This output will
be negated when the Receive PLCP Processor reaches the “In Frame” Condi-
tion.
N
OTE
:
This output pin is only active if the user has configured the XRT72L71
to operate in the “ATM UNI” Mode.
107
TxFrameRef
I
Transmit DS3 Framer—Frame Reference Input Pin:
The Transmit DS3
Framer can be configured to use this input signal as the “framing” reference for
the Transmit DS3 Framer block. If this input pin is chosen to be the timing ref-
erence, then any rising edge at this input will cause the Transmit DS3 Framer
to begin its creation a new DS3 M-frame. Consequently, the user must supply
a clock signal that is equivalent to the DS3 Frame rate (or 9398.3 Hz). Fur-
ther, the signal which is driving this input pin, must be synchronized witht he
44.736MHz clock signal, which is applied to the “TxInClk” input pin.
N
OTE
:
This input pin should be tied to “GND” if it is not used as the Transmit
DS3 Framer frame reference signal.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
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| XRT72L71ES-00PCI | 功能描述:網絡控制器與處理器 IC T73LC00A+T71D00 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L71IQ | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L71IQ-F | 功能描述:網絡控制器與處理器 IC Single CH DS3 UNI (3.3V) RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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