參數(shù)資料
型號： XRT86VL32IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： DATACOM, FRAMER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù)： 114/174頁
文件大小： 903K
代理商： XRT86VL32IB
XRT86VL32
109
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
4
COFA Status
RUR/
WC
0
Change of FAS Framing Alignment (COFA) Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change of
FAS Framing Alignment” interrupt has occurred since the last read of this
register.
If this interrupt is enabled, then the Receive E1 Framer block will
generate an interrupt whenever the Receive E1 Framer block detects a
Change of FAS Framing Alignment Signal (e.g., the FAS bits have
appeared to move to a different location within the incoming E1 data
stream).
0 = Indicates that the “Change of FAS Framing Alignment (COFA)” inter-
rupt has not occurred since the last read of this register.
1 = Indicates that the “Change of FAS Framing Alignment (COFA)” inter-
rupt has occurred since the last read of this register.
3
OOF Status
RUR/
WC
0
Change in Out of Frame Defect Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Out of Frame Defect Condition” interrupt has occurred since the
last read of this register.
Out of Frame defect condition is declared when “FASC” number of consec-
utive errored FAS patterns are detected, where “FASC” indicates the Loss
of FAS Alignment Criteria in the Framing Control Register (0xn10B), bit 2-
0.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive E1 Framer block declares the Out of Frame
defect condition.
2.
Whenever the Receive E1 Framer block clears the Out of Frame
defect condition
0 = Indicates that the “Change in Receive Out of Frame defect condition”
interrupt has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Out of Frame defect condition”
interrupt has occurred since the last read of this register
2
FMD Status
RUR/
WC
0
Frame Mimic Detection Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Frame Mimic
Detection” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive E1 Framer block will
generate an interrupt whenever the Receive E1 Framer block detects the
presence of Frame Mimic bits (i.e., the Payload bits have appeared to
mimic the Framing pattern within the incoming E1 data stream).
0 = Indicates that the “Frame Mimic Detection” interrupt has not occurred
since the last read of this register.
1 = Indicates that the “Frame Mimic Detection” interrupt has occurred since
the last read of this register.
T
ABLE
97: F
RAMER
I
NTERRUPT
S
TATUS
R
EGISTER
(FISR) H
EX
A
DDRESS
: 0
X
nB04
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
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參數(shù)描述
XRT86VL32IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 1-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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