參數(shù)資料
型號： XRT86VL32IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： DATACOM, FRAMER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù)： 14/174頁
文件大?。?/td> 903K
代理商： XRT86VL32IB
XRT86VL32
9
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
1.0
REGISTER DESCRIPTIONS - E1 MODE
All address on this register description is shown in HEX format, where n indicates channels 0 and 2 in the
2-channel device.
T
ABLE
2: C
LOCK
S
ELECT
R
EGISTER
(CSR) H
EX
A
DDRESS
: 0
X
n100
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
LCV Insert
R/W
0
Line Code Violation Insertion
This bit is used to force a Line Code Violation (LCV) on the transmit
output of TTIP/TRING.
A “0” to “1” transition on this bit will cause a single LCV to be inserted
on the transmit output of TTIP/TRING.
6
Set T1 Mode
R/W
0
T1/E1 Mode select
This bit is used to program the individual channel to operate in either
T1 or E1 mode.
0 = Configures the selected channel to operate in E1 mode.
1 = Configures the selected channel to operate in T1 mode.
5
Sync All Transmit-
ters to 8kHz
R/W
0
Sync All Transmit Framers to 8kHz
This bit permits the user to configure each of the two (2) Transmit E1
Framer blocks to synchronize their “transmit output” frame alignment
with the 8kHz signal that is derived from the MCLK PLL, as described
below.
0 - Disables the “Sync all Transmit Framers to 8kHz” feature for all 2
channels.
1 - Enables the “Sync all Transmit Framers to 8kHz” feature for all 2
channels.
N
OTE
:
Writing to this bit in register 0x0100 will enable this feature for
all 2 channels.
N
OTE
:
This bit is only active if the MCLK PLL is used as the “Timing
Source” for the Transmit E1 Framer” blocks. CSS[1:0] of this
register allows users to select the transmit source of the
framer.
4
Clock Loss Detect
R/W
1
Clock Loss Detect Enable/Disable Select
This bit enables a clock loss protection feature for the Framer when-
ever the recovered line clock is used as the timing source for the trans-
mit section. If the LIU loses clock recovery, the Clock Distribution Block
will detect this occurrence and automatically begin to use the internal
clock derived from MCLK PLL as the Transmit source, until the LIU is
able to regain clock recovery.
0 = Disables the clock loss protection feature.
1 = Enables the clock loss protection feature.
N
OTE
:
This bit needs to be enabled in order to detect the clock loss
detection interrupt status (address: 0xnB00, bit 5)
3:2
Reserved
R/W
00
Reserved
相關(guān)PDF資料
PDF描述
XRT86VL34_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL32IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 1-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*