參數(shù)資料
型號(hào)： XRT86VL32IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： DATACOM, FRAMER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù)： 162/174頁
文件大小： 903K
代理商： XRT86VL32IB
XRT86VL32
157
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
122: LIU C
HANNEL
C
ONTROL
I
NTERRUPT
S
TATUS
R
EGISTER
(LIUCCISR) H
EX
A
DDRESS
: 0
X
0F
N
6
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
RO
0
6
DMOIS_n
RUR/
WC
0
Change of Transmit DMO (Drive Monitor Output) Condition
Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change of
the Transmit DMO Condition” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when DMO_n status bit (bit 6
of Register 0x0Fn5) has changed since the last read of this
register.
N
OTE
:
Users can determine the current state of the “Transmit DMO
Condition” by reading out the content of bit 6 within Register
0x0Fn5
5
FLSIS_n
RUR/
WC
0
FIFO Limit Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “FIFO
Limit” Interrupt has occurred since the last read of this register.
0 = Indicates that the “FIFO Limit Status” Interrupt has NOT
occurred since the last read of this register.
1 = Indicates that the “FIFO Limit Status” Interrupt has occurred
since the last read of this register.
This bit is set to a “1” every time when FIFO Limit Status bit
(bit 5 of Register 0x0Fn5) has changed since the last read of
this register.
N
OTE
:
Users can determine the current state of the “FIFO Limit” by
reading out the content of bit 5 within Register 0x0Fn5
4
Reserved
-
-
This bit is not used
3
NLCDIS_n
RUR/
WC
0
Change in Network Loop-Code Detection Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change in
Network Loop-Code Detection” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when NLCD status bit (bit 3 of Reg-
ister 0x0Fn5) has changed since the last read of this register.
N
OTE
:
Users can determine the current state of the “Network Loop-
Code Detection” by reading out the content of bit 3 within
Register 0x0Fn5
2
Reserved
-
-
This bit is not used
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL32IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 1-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL34_07 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL34_1 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL34_2 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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